Bug 97204 - [IVB] Can't enable a third monitor even with 3 CRTCs available (1 LVDS, 1 VGA, 1 HDMI/VGA)
Summary: [IVB] Can't enable a third monitor even with 3 CRTCs available (1 LVDS, 1 VGA...
Status: CLOSED FIXED
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: unspecified
Hardware: x86-64 (AMD64) Linux (All)
: medium normal
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2016-08-04 15:50 UTC by Nick Yamane
Modified: 2017-07-24 22:40 UTC (History)
2 users (show)

See Also:
i915 platform: IVB
i915 features: display/Other


Attachments
dmesg output with drm.debug enabled (211.97 KB, text/plain)
2016-08-04 15:50 UTC, Nick Yamane
no flags Details
[PATCH] drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED (3.04 KB, patch)
2016-08-04 16:38 UTC, Ville Syrjala
no flags Details | Splinter Review
[PATCH] drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED (linux 4.4.16) (3.04 KB, patch)
2016-08-04 21:43 UTC, Nick Yamane
no flags Details | Splinter Review
dmesg output with patch applied and drm.debug=0xe (201.47 KB, text/plain)
2016-09-21 19:00 UTC, Nick Yamane
no flags Details

Description Nick Yamane 2016-08-04 15:50:27 UTC
Created attachment 125534 [details]
dmesg output with drm.debug enabled

I'm running Arch Linux - kernel 4.6.4 and also tested with 4.4.16 - on a laptop Lenovo Ideapad Z400, which has 2 GPUs, 1 NVIDEA (disabled) and 1 Intel. Connected 2 external monitors, 1 via VGA and the other via HDMI using a HDMI/DVI connector. The problem occurs when I try to enable a third display, xrandr fails with the message "Configure crtc 2 failed". Already checked and it seems to have 3 CRTCs hardware available. Running kernel with "drm.debug=0xe" (dmesg attached) it shows "[  339.630668] [drm:ironlake_crtc_compute_clock] failed to find PLL for pipe C" at some point.
This seems to be similar or a regression of https://bugs.freedesktop.org/show_bug.cgi?id=68485, not sure.

Thanks for your help. Please let me know if there's anything I can do to help in debugging/testing.
Comment 1 Chris Wilson 2016-08-04 15:58:34 UTC
That's a classic IVB. It only has 2 PLL, but 3 pipes. In order to use the third pipe, it must exactly match the frequency of one of the other two.
Comment 2 Nick Yamane 2016-08-04 16:11:08 UTC
Hi Chris,
Sorry, not sure if I got it. So it's not a bug?
The frequency you told is the same that can be set via xrand stuff ?
Thanks
Comment 3 Ville Syrjala 2016-08-04 16:38:06 UTC
Created attachment 125537 [details] [review]
[PATCH] drm/i915: Allow PCH DPLL sharing regardless of  DPLL_SDVO_HIGH_SPEED

This patch will allow DPLL sharing between VGA and HDMI. However it won't help you unless you make both VGA and HDMI use the same exact mode. In your log I see the modes were slightly different. So you'll need make sure that happens, and then hope that both monitors will sync with the same mode.
Comment 4 Nick Yamane 2016-08-04 17:02:27 UTC
(In reply to Ville Syrjala from comment #3)
> Created attachment 125537 [details] [review] [review]
> [PATCH] drm/i915: Allow PCH DPLL sharing regardless of  DPLL_SDVO_HIGH_SPEED
> 
> This patch will allow DPLL sharing between VGA and HDMI. However it won't
> help you unless you make both VGA and HDMI use the same exact mode. In your
> log I see the modes were slightly different. So you'll need make sure that
> happens, and then hope that both monitors will sync with the same mode.

Thanks. I'll test it and give you feedback about it soon. :)
Comment 5 Nick Yamane 2016-08-04 18:42:33 UTC
(In reply to Ville Syrjala from comment #3)
> Created attachment 125537 [details] [review] [review]
> [PATCH] drm/i915: Allow PCH DPLL sharing regardless of  DPLL_SDVO_HIGH_SPEED
> 
> This patch will allow DPLL sharing between VGA and HDMI. However it won't
> help you unless you make both VGA and HDMI use the same exact mode. In your
> log I see the modes were slightly different. So you'll need make sure that
> happens, and then hope that both monitors will sync with the same mode.

Which kernel tree should I use to apply your patch? tried with the mainline one and got this error:

drivers/gpu/drm/i915/intel_display.c: In function ‘ironlake_compute_dpll’:
drivers/gpu/drm/i915/intel_display.c:8903:6: error: implicit declaration of function ‘intel_crtc_has_type’ [-Werror=implicit-function-declaration]
      intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
      ^~~~~~~~~~~~~~~~~~~
Comment 6 Nick Yamane 2016-08-04 21:43:55 UTC
Created attachment 125546 [details] [review]
[PATCH] drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED (linux 4.4.16)

It worked. Just modified your patch to be able to apply in my kernel (v4.4.14 LTS), using "intel_pipe_has_type" instead of "intel_crtc_has_type". Is that correct?

+       if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
+           intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_ANALOG))
+               dpll |= DPLL_SDVO_HIGH_SPEED;
+
Comment 7 Ville Syrjala 2016-08-09 10:55:05 UTC
(In reply to Nick Yamane from comment #6)
> Created attachment 125546 [details] [review] [review]
> [PATCH] drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED
> (linux 4.4.16)
> 
> It worked. Just modified your patch to be able to apply in my kernel
> (v4.4.14 LTS), using "intel_pipe_has_type" instead of "intel_crtc_has_type".
> Is that correct?
> 
> +       if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
> +           intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_ANALOG))
> +               dpll |= DPLL_SDVO_HIGH_SPEED;
> +

Almost correct. intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)
is what should be used on 4.4. Can you double check with that?

Actually can you also attach a dmesg (w/ drm.debug=0xe) with the patch applied? I'd like to see that it really enables three pipes. In theory it might just setup a clone between HDMI and VGA and use just one pipe for both). That may happen if you don't specify a unique x/y position for each output, and the outputs are using the same mode.
Comment 8 Ville Syrjala 2016-09-20 14:04:14 UTC
(In reply to Ville Syrjala from comment #7)
> (In reply to Nick Yamane from comment #6)
> > Created attachment 125546 [details] [review] [review] [review]
> > [PATCH] drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED
> > (linux 4.4.16)
> > 
> > It worked. Just modified your patch to be able to apply in my kernel
> > (v4.4.14 LTS), using "intel_pipe_has_type" instead of "intel_crtc_has_type".
> > Is that correct?
> > 
> > +       if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
> > +           intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_ANALOG))
> > +               dpll |= DPLL_SDVO_HIGH_SPEED;
> > +
> 
> Almost correct. intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)
> is what should be used on 4.4. Can you double check with that?
> 
> Actually can you also attach a dmesg (w/ drm.debug=0xe) with the patch
> applied? I'd like to see that it really enables three pipes. In theory it
> might just setup a clone between HDMI and VGA and use just one pipe for
> both). That may happen if you don't specify a unique x/y position for each
> output, and the outputs are using the same mode.

Ping?
Comment 9 Nick Yamane 2016-09-20 15:33:11 UTC
Hello, sorry for the delay. I'm out of office right now, but I've applied the patch some weeks ago, it worked but if I can recall I experienced some issues. Anyway, I'll try to test it again later today and will post the logs here. Btw, the patch has already landed somewhere upstream? Or I still need to apply it manually and compile i915 module by myself?
Thanks
Comment 10 Nick Yamane 2016-09-21 19:00:18 UTC
Created attachment 126714 [details]
dmesg output with patch applied and drm.debug=0xe

Hi Ville Syrjala,

Just tested here, with your patch applied to my 4.7.4 kernel (on Arch Linux) running Awesome WM, and it's working quite well for now. Attached my dmesg log with drm.debug=0xe as you asked.

Thanks for your great help! Hope it's working as you expected.
Comment 11 yann 2016-09-27 07:44:57 UTC
Adding reference to submitted patch: https://patchwork.freedesktop.org/series/12918/
Comment 12 Ville Syrjala 2016-09-28 14:19:33 UTC
Fix pushed

commit 7d7f8633a82763577727762ff3ac1df3017cb8fe
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Mon Sep 26 11:30:46 2016 +0300

    drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED


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