Attachment 68396 Details for Bug 55834 – Patch for solution b.

[patch] Patch for solution b.

On-GEN2-map-GTT-Aperture-non-cached.patch (text/plain), 1.15 KB, created by Egbert Eich on 2012-10-10 10:15:16 UTC

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Creator: Egbert Eich

Created: 2012-10-10 10:15:16 UTC

Size: 1.15 KB

patch

obsolete

>From: Egbert Eich <eich@suse.com>
>Date: Tue Oct 9 16:48:46 2012 +0200
>Subject: On GEN2 map GTT Aperture non-cached.
>Git-commit: cd2d616af9825e8b0986d7d26d25209ed80b9d72
>Signed-off-by: Egbert Eich <eich@suse.de>
>
>On GEN2 the GTT aperture sits on the same BAR as the
>MMIO registers right in the middle of that range.
>The Intel driver maps the entire BAR uncached to
>have access to all registers.
>This does not work if the intel-gtt module has mapped
>the GTT aperture WC.
>A simple workaround is to map the GTT uncached also.
>
>Signed-off-by: Egbert Eich <eich@sles11.fritz.box>
>---
> drivers/char/agp/intel-gtt.c |    2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
>diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
>index e01f5ea..797af72 100644
>--- a/drivers/char/agp/intel-gtt.c
>+++ b/drivers/char/agp/intel-gtt.c
>@@ -667,7 +667,7 @@ static int intel_gtt_init(void)
> 	gtt_map_size = intel_private.base.gtt_total_entries * 4;
> 
> 	intel_private.gtt = NULL;
>-	if (INTEL_GTT_GEN < 6)
>+	if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN != 2)
> 		intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
> 					       gtt_map_size);
> 	if (intel_private.gtt == NULL)

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