Bug 111645

Summary: [CI][RESUME] igt@gem_mocs_settings@mocs-settings-.*-render - fail - Failed assertion: read_regs[index] & 0xffff == table.table[index * 2].l3cc_value
Product: DRI Reporter: Martin Peres <martin.peres>
Component: DRM/IntelAssignee: Intel GFX Bugs mailing list <intel-gfx-bugs>
Status: RESOLVED DUPLICATE QA Contact: Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity: not set    
Priority: high CC: intel-gfx-bugs
Version: XOrg git   
Hardware: Other   
OS: All   
Whiteboard:
i915 platform: TGL i915 features: GEM/Other

Description Martin Peres 2019-09-11 07:26:11 UTC 
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html

Starting subtest: mocs-settings-ctx-render
(gem_mocs_settings:1032) CRITICAL: Test assertion failure function check_l3cc_registers, file ../tests/i915/gem_mocs_settings.c:411:
(gem_mocs_settings:1032) CRITICAL: Failed assertion: read_regs[index] & 0xffff == table.table[index * 2].l3cc_value
(gem_mocs_settings:1032) CRITICAL: error: 0x13 != 0x30
Comment 1 CI Bug Log 2019-09-11 07:26:36 UTC 
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: igt@gem_mocs_settings@mocs-settings-.*-render - fail - Failed assertion: read_regs[index] &amp; 0xffff == table.table[index * 2].l3cc_value
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_365/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_362/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_362/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_365/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_365/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html
Comment 2 prathap.kumar.valsan 2019-09-19 13:34:18 UTC 
This test is passing by its own.
Any mocs tests ran after *-reset-* tests are failing. Because after a reset, the mocs values are not getting re-initialized. 

So i believe probably we should re-run all mocs tests without including *-reset-* tests and have one BUG filed to investigate the reset flow.
Comment 3 prathap.kumar.valsan 2019-09-19 13:34:56 UTC 

*** This bug has been marked as a duplicate of bug 111723 ***

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