The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: igt@gem_mocs_settings@mocs-.*-render - fail - Failed assertion: read_regs[index] & 0xffff == table.table[index * 2].l3cc_value
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_366/fi-tgl-u/igt@gem_mocs_settings@mocs-rc6-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_mocs_settings@mocs-isolation-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_mocs_settings@mocs-isolation-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u/igt@gem_mocs_settings@mocs-rc6-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_mocs_settings@mocs-isolation-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_369/fi-tgl-u2/igt@gem_mocs_settings@mocs-rc6-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_mocs_settings@mocs-isolation-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u/igt@gem_mocs_settings@mocs-rc6-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_mocs_settings@mocs-isolation-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_370/fi-tgl-u2/igt@gem_mocs_settings@mocs-rc6-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u/igt@gem_mocs_settings@mocs-rc6-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_mocs_settings@mocs-isolation-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_371/fi-tgl-u2/igt@gem_mocs_settings@mocs-rc6-ctx-render.html

It reports discrepancy between HW register and internally hard coded table as follow.

static const struct mocs_entry tigerlake_mocs_table[GEN11_NUM_MOCS_ENTRIES] = {
	[2]  = { 0x00000037, 0x0030, 0x1},
....

I am not sure its size, GEN11_NUM_MOCS_ENTRIES is TIGERLAKE_NUM_MOCS_ENTRIES.

Anyway, this is another test which is not ready for TGL.

This test is passing.
Any mocs tests ran after *-reset-* tests are failing. Because after a reset, the mocs values are not getting re-initialized. 

So i believe probably we should re-run all mocs tests without including *-reset-* tests and have one BUG filed to investigate the reset flow.

*** Bug 111645 has been marked as a duplicate of this bug. ***

commit eca0b72089695d5b19c8c2b287ac3f6fbe79197e (HEAD -> drm-intel-next-queued, drm-intel/drm-intel-next-queued)
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Oct 16 10:07:49 2019 +0100

    drm/i915: Do initial mocs configuration directly
    
    Now that we record the default "goldenstate" context, we do not need to
    emit the mocs registers at the start of each context and can simply do
    mmio before the first context and capture the registers as part of its
    default image. As a consequence, this means that we repeat the mmio
    after each engine reset, fixing up any platform and registers that were
    zapped by the reset (for those platforms with global not context-saved
    settings).
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111723
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111645
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
    Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
    Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20191016090749.7092-1-chris@chris-wilson.co.uk