Bug 111645 - [CI][RESUME] igt@gem_mocs_settings@mocs-settings-.*-render - fail - Failed assertion: read_regs[index] & 0xffff == table.table[index * 2].l3cc_value
Summary: [CI][RESUME] igt@gem_mocs_settings@mocs-settings-.*-render - fail - Failed as...
Status: NEW
Alias: None
Product: DRI
Classification: Unclassified
Component: DRM/Intel (show other bugs)
Version: XOrg git
Hardware: Other All
: high not set
Assignee: Intel GFX Bugs mailing list
QA Contact: Intel GFX Bugs mailing list
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2019-09-11 07:26 UTC by Martin Peres
Modified: 2019-09-11 07:26 UTC (History)
1 user (show)

See Also:
i915 platform: TGL
i915 features: GEM/Other


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Description Martin Peres 2019-09-11 07:26:11 UTC
https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html

Starting subtest: mocs-settings-ctx-render
(gem_mocs_settings:1032) CRITICAL: Test assertion failure function check_l3cc_registers, file ../tests/i915/gem_mocs_settings.c:411:
(gem_mocs_settings:1032) CRITICAL: Failed assertion: read_regs[index] & 0xffff == table.table[index * 2].l3cc_value
(gem_mocs_settings:1032) CRITICAL: error: 0x13 != 0x30
Comment 1 CI Bug Log 2019-09-11 07:26:36 UTC
The CI Bug Log issue associated to this bug has been updated.

### New filters associated

* TGL: igt@gem_mocs_settings@mocs-settings-.*-render - fail - Failed assertion: read_regs[index] & 0xffff == table.table[index * 2].l3cc_value
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_365/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_362/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_362/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_365/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_365/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14335/re-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_363/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-ctx-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-reset-render.html
  - https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_364/fi-tgl-u/igt@gem_mocs_settings@mocs-settings-render.html


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