Bug 55834

Summary: gen2 regression] Current i915 DRM driver fails on GEN2 hardware (i845).
Product: DRI Reporter: Egbert Eich <eich>
Component: DRM/IntelAssignee: Daniel Vetter <daniel>
Status: CLOSED FIXED QA Contact:
Severity: normal    
Priority: medium CC: ben, chris, daniel, jbarnes, rodrigo.vivi
Version: XOrg git   
Hardware: x86 (IA32)   
OS: Linux (All)   
i915 platform: i915 features:
Description Flags
Patch for solution a.
Patch for solution b. none

Description Egbert Eich 2012-10-10 10:14:28 UTC
Created attachment 68395 [details] [review]
Patch for solution a.

The DRM driver from drm-intel-next currently fails to initialize on GEN2 hardware.
Reason: the intel_gtt module maps the GTT aperture WC. This aperture however is located right in the middle of BAR 1 (where the MMIO registers are located). When the i915 driver loads it tries to map the entire bar uncached which conflicts with the earlier mapping in intel_gtt.
There are two ways to fix this:

a. map the lower and upper MMIO register ranges separately and adjust the 
   access functions accordingly. (elaborate patch).  
b. map the GTT aperture uncached (tiny patch).

(See attachments)
Comment 1 Egbert Eich 2012-10-10 10:15:16 UTC
Created attachment 68396 [details] [review]
Patch for solution b.
Comment 2 Chris Wilson 2012-10-10 10:24:05 UTC
Not all gen2 are affected, the wc mapping works on 855gm. But disabling it is the simplest patch.. :|
Comment 3 Egbert Eich 2012-10-10 20:25:09 UTC
(In reply to comment #2)
> Not all gen2 are affected, the wc mapping works on 855gm. But disabling it
> is the simplest patch.. :|

This only seems to happen when PAT support is enabled. 
Chris, could you please check if you get a "PAT not supported by CPU" on your system?

This is at least what happens here on my i855 test system where I don't see the issue either.
Comment 4 Chris Wilson 2012-10-10 21:57:47 UTC
No PAT on my gen2 systems either. Okay, now that is bizarre.
Comment 5 Daniel Vetter 2012-10-10 22:11:54 UTC
Yeah, my i855gm also doesn't support PAT. I guess we simply need to disable the wc gtt pte mapping on gen2, not worth the trouble.
Comment 6 Chris Wilson 2012-10-12 21:11:02 UTC
What's behind door number 2?

commit 9169d3a88072b20f42e68a946e916bd7dfbc7f2c
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Wed Oct 10 23:14:01 2012 +0200

    drm/i915: disable wc gtt pte mappings on gen2
    It doesn't work since the gtt pte range sits in the middle of the mmio
    bar. We didn't notice that since both my and Chris' gen2 machines
    don't support PAT and hence all wc io mapping request will
    automatically be demoted to uc.
    This regression has been introduce in
    commit edef7e685da05c13cce50c0126189c80fe2c8f71
    Author: Chris Wilson <chris@chris-wilson.co.uk>
    Date:   Fri Sep 14 11:57:47 2012 +0100
        agp/intel: Use a write-combining map for updating PTEs
    Reported-by: Egbert Eich <eich@pdx.freedesktop.org>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55834
    Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
    Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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