| Summary: | [BayTrail-M] [drm:intel_pipe_config_compare] *ERROR* mismatch in clock (expected 146250, found 0) | ||||||||||||||||
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| Product: | DRI | Reporter: | Guang Yang <guang.a.yang> | ||||||||||||||
| Component: | DRM/Intel | Assignee: | Jesse Barnes <jbarnes> | ||||||||||||||
| Status: | CLOSED FIXED | QA Contact: | Intel GFX Bugs mailing list <intel-gfx-bugs> | ||||||||||||||
| Severity: | normal | ||||||||||||||||
| Priority: | medium | CC: | cancan.feng, chris, evawang, james.ausmus | ||||||||||||||
| Version: | unspecified | ||||||||||||||||
| Hardware: | All | ||||||||||||||||
| OS: | All | ||||||||||||||||
| Whiteboard: | |||||||||||||||||
| i915 platform: | i915 features: | ||||||||||||||||
| Attachments: |
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Description
Guang Yang
2013-07-26 09:37:48 UTC
Clock mismatch is for Jesse. Created attachment 83120 [details] [review] Prototype vlv_crtc_clock_get Created attachment 83121 [details] [review] Prototype vlv_crtc_clock_get any progress? Chris, do you need QA to try your patch? Yup, a quick testrun of that patch would be good. Dmesg doesn't seem to have drm.debug enabled. - Please attach a drm.debug dmesg with the backtrace - Is this the same as bug #69248 i.e. only happens when edp is enabled, but not when only vga (or other ports) are enabled? (In reply to comment #3) > Created attachment 83121 [details] [review] [review] > Prototype vlv_crtc_clock_get Hi, I applied this patch on latest -next-queued kernel but can't build successfully. (In reply to comment #6) > Dmesg doesn't seem to have drm.debug enabled. > - Please attach a drm.debug dmesg with the backtrace > - Is this the same as bug #69248 i.e. only happens when edp is enabled, but > not when only vga (or other ports) are enabled? This "[drm:intel_pipe_config_compare] *ERROR* mismatch in clock" happens both on eDP and VGA. Created attachment 85894 [details]
the whole system booting dmesg
Created attachment 86104 [details]
wip vlv clock get patch
Chris, can you try this one out? My system is busted atm. It probably needs fixes to the calculations, but my system died right as I was about to try it.
Chris, please see last patch. Please test these two patches: http://lists.freedesktop.org/archives/intel-gfx/2013-September/033543.html (In reply to comment #12) > Please test these two patches: > > http://lists.freedesktop.org/archives/intel-gfx/2013-September/033543.html I can't apply this patch on latest -next-queued and -nightly, can you re-check it? Updated version of the patch (only one patch now): https://patchwork.kernel.org/patch/2920201/ Created attachment 86335 [details] dmesg: error also exists (In reply to comment #14) > Updated version of the patch (only one patch now): > > https://patchwork.kernel.org/patch/2920201/ I have tested this patch on latest -next-queued, and this error also exists. dmesg is appended here. Using the latest patch, I get found=8551, expected=138530 Hmm, 'tis working now.
[10412.590966] mdiv=11625351, m1=3, m2=81, n=5, p1=3, p2=2
[10412.590973] vco=4860000, dot=1620000, clock=162000
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5741d48..5219fdc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5083,10 +5083,10 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ const int refclk = 100000;
int pipe = pipe_config->cpu_transcoder;
intel_clock_t clock;
u32 mdiv;
- int refclk = 100000, fastclk, update_rate;
mutex_lock(&dev_priv->dpio_lock);
mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
@@ -5098,12 +5098,16 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
- update_rate = refclk / clock.n;
- clock.vco = update_rate * clock.m1 * clock.m2;
- fastclk = clock.vco / clock.p1 / clock.p2;
- clock.dot = (2 * fastclk);
+printk("mdiv=%x, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n",
+mdiv, clock.m1, clock.m2, clock.n, clock.p1, clock.p2);
+
+ clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
+ clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
pipe_config->port_clock = clock.dot / 10;
+
+printk("vco=%d, dot=%d, clock=%d\n",
+clock.vco, clock.dot, pipe_config->port_clock);
}
Fixed by: 58fc1e077db44f7ed13943426bb38c8e2740b7cc and 75b6ef3a51672c2cb25a100860df22e3688c00a6 (In reply to comment #18) > Fixed by: > 58fc1e077db44f7ed13943426bb38c8e2740b7cc and > 75b6ef3a51672c2cb25a100860df22e3688c00a6 OK, this error disappeared, verified here. Bug 69248 - [Baytrail-M] mismatch in clock for eDP is the same with this bug. Closing old verified. |
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