Bug 106148 - [CI][GLK] Ubuntu 18.04 (pre-release) fails piglit variable-indexing tests
Summary: [CI][GLK] Ubuntu 18.04 (pre-release) fails piglit variable-indexing tests
Status: CLOSED WORKSFORME
Alias: None
Product: Mesa
Classification: Unclassified
Component: Drivers/DRI/i965 (show other bugs)
Version: 18.0
Hardware: x86-64 (AMD64) Linux (All)
: medium normal
Assignee: Intel 3D Bugs Mailing List
QA Contact: Intel 3D Bugs Mailing List
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Keywords:
Depends on:
Blocks:
 
Reported: 2018-04-20 12:49 UTC by Tomi Sarvela
Modified: 2018-09-04 10:19 UTC (History)
2 users (show)

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Description Tomi Sarvela 2018-04-20 12:49:58 UTC
Hi,

We're adding piglit regression testing to Intel-GFX-CI. When running our testsets to get a good green baseline, an issue was found with Gemini Lake NUC: it fails a bunch of tests that didn't fail on SKL (6600) or HSW (4770r) on DRM-Tip kernels.

Hardware is Intel NUC7CJYH (J4005) 2 cores and 2x4GB memory

Distro is freshly installed Ubuntu 18.04 with todays updates, and kernel / mesa version reflects that:
wflinfo -p gbm -a gl: Mesa 18.0.0-rc5
uname -a: Linux 4.15.0-12-generic or (for example) 4.17.0-rc1-CI-CI_DRM_4069

Example of the piglit invocation:
$ ./piglit run tests/gpu ~/results -p gbm -t spec@arb_tessellation_shader@execution@variable-indexing@

Specific information can be gleaned from

https://intel-gfx-ci.01.org/tree/drm-tip/piglit-issues.html

CI_DRM_4069 is the last kernel without all the blacklisting on.

Tests below fail on all hosts with default Ubuntu kernel, and
they fail on GLK when using DRM-Tip kernel (this needs confirmation):

spec@arb_tessellation_shader@execution@1in-1out
spec@arb_tessellation_shader@execution@dmat-vs-gs-tcs-tes
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-float-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-vec2-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-vec3-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-input-array-vec4-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-rd-after-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-wr
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-wr-before-barrier
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-float-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-vec2-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-vec3-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-both-input-array-vec4-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-float-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-vec2-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-vec3-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@tes-input-array-vec4-index-rd
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-float-index-wr-before-tcs
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec2-index-wr-before-tcs
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec4-index-wr-before-tcs
spec@glsl-1.50@execution@geometry@end-primitive
spec@glsl-1.50@execution@geometry@max-input-components
spec@glsl-1.50@execution@variable-indexing@gs-input-array-vec3-index-rd
spec@glsl-1.50@execution@variable-indexing@gs-input-array-vec4-index-rd
spec@glsl-1.50@execution@variable-indexing@vs-output-array-vec3-index-wr-before-gs
spec@glsl-1.50@gs-max-output-components

Note that Ubuntu 18.04 and the mesa version is still moving around, and kernel is just-released -RC1, so this could be just a fluke on our systems. I'll open the bug anyway for investigation because reproduction should be easy.
Comment 1 Kenneth Graunke 2018-04-20 16:59:13 UTC
Huh, that sounds like something that would've been fixed by 8eadc2fb8fe395ea0a8202217bd5545978962d1d, but you've got that already.

Thanks for the report.
Comment 2 Mark Janes 2018-04-20 18:13:07 UTC
These tests have been passing for us in mesa ci on GLK:

http://otc-mesa-ci.jf.intel.com/job/mesa_master_daily/4050/testReport/piglit.spec.arb_tessellation_shader.execution/variable-indexing/

4.15.4 debian kernel
Comment 3 Tomi Sarvela 2018-04-23 13:45:29 UTC
The issue on GLKs is stable from kernel to kernel.

For now, I'm assuming that the failing component is Ubuntu's compilation of Mesa 18.0.0-rc5. I'm leaving couple of tests from this list whitelisted to see when they are passing again, and will mark those tests with this bug ID when CI Bug Log can handle it.
Comment 4 Tomi Sarvela 2018-05-04 13:28:08 UTC
GLK-J5005 "Pentium" passes the following tests that J4005 "Celeron" failed:

spec@glsl-1.50@execution@geometry@end-primitive 0
spec@glsl-1.50@gs-max-output-components

Hardware is NUC7CJYH and NUC7PJYH
Comment 5 Tomi Sarvela 2018-05-04 13:37:43 UTC
Also all the other tests that J4005 failed, J5005 passes.

https://intel-gfx-ci.01.org/tree/drm-tip/piglit-issues.html

Memory and harddisk was moved from J4005 to J5005, change happened at CI_DRM_4145.
Comment 6 Martin Peres 2018-06-19 21:56:49 UTC
(In reply to Tomi Sarvela from comment #5)
> Also all the other tests that J4005 failed, J5005 passes.
> 
> https://intel-gfx-ci.01.org/tree/drm-tip/piglit-issues.html
> 
> Memory and harddisk was moved from J4005 to J5005, change happened at
> CI_DRM_4145.

I cannot see this failing since CI_DRM_4144_full (1 month, 2 weeks / 760 runs ago). Is it because we stopped running the tests or dropped this machine, or is the problem fixed?
Comment 7 Tomi Sarvela 2018-06-20 07:11:06 UTC
We do have J5005 now in CI, which doesn't show the issue. As mentioned in the comments.

With J4005 (two-core GLK) NUC the issue was easily reproducible, but that was too slow to run the testset.
Comment 8 Mark Janes 2018-06-20 14:40:39 UTC
We found many depth/stencil tests that failed for 2x6 that do not fail for 3x6, tracked in

https://bugs.freedesktop.org/show_bug.cgi?id=106865

They are intermittent, but easy to reproduce.  Nanley and Ken have taken a look but failed to find any issue with Mesa's configuration of that sku, or documented workarounds.

Tomi: do the tesselation failures occur when tests are run individually/serially?  Depth/stencil failures occur when run in parallel.  Do you see bug 106865 in your CI results for this system?

Clayton: can you build a drm-tip kernel for the 2x6 and check both the depth/stencil and tesselation tests?
Comment 9 Martin Peres 2018-09-04 10:18:25 UTC
(In reply to Tomi Sarvela from comment #7)
> We do have J5005 now in CI, which doesn't show the issue. As mentioned in
> the comments.
> 
> With J4005 (two-core GLK) NUC the issue was easily reproducible, but that
> was too slow to run the testset.

Since we can't reproduce the problem because we don't run on this machine anymore, let's close the bug.


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