https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6921/fi-tgl-u/igt@i915_selftest@live_gtt.html (i915_selftest:4191) igt_kmod-WARNING: igt_cs_tlb failed with error -22 (i915_selftest:4191) igt_kmod-WARNING: ntel_power_well_enable [i915]] enabling always-on (i915_selftest:4191) igt_kmod-WARNING: ntel_power_well_enable [i915]] enabling DC off (i915_selftest:4191) igt_kmod-WARNING: en9_set_dc_state [i915]] Setting DC state from 02 to 00 (i915_selftest:4191) igt_kmod-WARNING: ntel_combo_phy_init [i915]] Combo PHY A already enabled, won't reprogram it. (i915_selftest:4191) igt_kmod-WARNING: ntel_combo_phy_init [i915]] Combo PHY B already enabled, won't reprogram it. (i915_selftest:4191) igt_kmod-WARNING: ntel_power_well_enable [i915]] enabling power well 2 (i915_selftest:4191) igt_kmod-WARNING: ntel_power_well_enable [i915]] enabling power well 3 (i915_selftest:4191) igt_kmod-WARNING: ntel_power_well_enable [i915]] enabling power well 4 (i915_selftest:4191) igt_kmod-WARNING: ntel_power_well_enable [i915]] enabling power well 5 (i915_selftest:4191) igt_kmod-WARNING: probe of 0000:00:02.0 failed with error -22 (i915_selftest:4191) igt_kmod-CRITICAL: Test assertion failure function igt_kselftest_execute, file ../lib/igt_kmod.c:532: (i915_selftest:4191) igt_kmod-CRITICAL: Failed assertion: err == 0 (i915_selftest:4191) igt_kmod-CRITICAL: kselftest "i915 igt__25__live_gtt=1 live_selftests=-1 disable_display=1 st_filter=" failed: Invalid argument [22] (i915_selftest:4191) igt_core-INFO: Stack trace: (i915_selftest:4191) igt_core-INFO: #0 ../lib/igt_core.c:1696 __igt_fail_assert() (i915_selftest:4191) igt_core-INFO: #1 ../lib/igt_kmod.c:535 igt_kselftest_execute() (i915_selftest:4191) igt_core-INFO: #2 [main+0x30] (i915_selftest:4191) igt_core-INFO: #3 [<unknown>+0xfe2b5100] **** END **** Subtest live_gtt: FAIL (15.143s) Dmesg-Warnings <3> [537.622691] i915/i915_gem_gtt_live_selftests: igt_cs_tlb failed with error -22
The CI Bug Log issue associated to this bug has been updated. ### New filters associated * TGL: igt@i915_selftest@live_gtt - dmesg-fail - igt_cs_tlb failed with error -22 - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5012/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5012/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5013/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14414/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14455/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14455/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6921/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6921/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6922/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6922/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14457/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14457/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14458/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14458/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6923/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6923/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14459/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14459/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6924/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6924/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14460/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14460/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5043/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5045/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_5045/fi-tgl-u2/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3481/fi-tgl-u/igt@i915_selftest@live_gtt.html - https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3481/fi-tgl-u2/igt@i915_selftest@live_gtt.html
commit c45e788d95b470e9f68fabe1f3cb44beb5dd7840 (HEAD -> drm-intel-next-queued, drm-intel/drm-intel-next-queued) Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Sep 19 16:18:11 2019 +0100 drm/i915/tgl: Suspend pre-parser across GTT invalidations Before we execute a batch, we must first issue any and all TLB invalidations so that batch picks up the new page table entries. Tigerlake's preparser is weakening our post-sync CS_STALL inside the invalidate pipe-control and allowing the loading of the batch buffer before we have setup its page table (and so it loads the wrong page and executes indefinitely). The igt_cs_tlb indicates that this issue can only be observed on rcs, even though the preparser is common to all engines. Alternatively, we could do TLB shootdown via mmio on updating the GTT. By inserting the pre-parser disable inside EMIT_INVALIDATE, we will also accidentally fixup execution that writes into subsequent batches, such as gem_exec_whisper and even relocations performed on the GPU. We should be careful not to allow this disable to become baked into the uABI! The issue is that if userspace relies on our disabling of the HW optimisation, when we are ready to enable that optimisation, userspace will then be broken... Testcase: igt/i915_selftests/live_gtt/igt_cs_tlb Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111753 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190919151811.9526-1-chris@chris-wilson.co.uk
*** Bug 111739 has been marked as a duplicate of this bug. ***
This issue was 100% reproducible till CI_DRM_6925 (8 days old). No new occurrence since, closing and archiving the bug.
The CI Bug Log issue associated to this bug has been archived. New failures matching the above filters will not be associated to this bug anymore.
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