Bug 14421 - x86-64 code is AMD specific (uses 3dnow! instructions not available on 64-bit intel chips)
Summary: x86-64 code is AMD specific (uses 3dnow! instructions not available on 64-bit...
Status: RESOLVED DUPLICATE of bug 8724
Alias: None
Product: Mesa
Classification: Unclassified
Component: Mesa core (show other bugs)
Version: unspecified
Hardware: x86-64 (AMD64) All
: medium blocker
Assignee: mesa-dev
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Reported: 2008-02-07 22:01 UTC by Priit Laes (irc: plaes)
Modified: 2008-02-08 05:34 UTC (History)
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Description Priit Laes (irc: plaes) 2008-02-07 22:01:24 UTC
I got a SIGILL in p4_3d_no_rot_loop () at x86-64/xform4.S:245.

That function (well, all of them in this file) contains prefetchw function.
prefetchw belongs to 3DNow! which is not present in 64-bit Intel chips such as mine:

plaes@chi ~ $ cat /proc/cpuinfo 
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 15
model name	: Intel(R) Core(TM)2 CPU         L7400  @ 1.50GHz
stepping	: 6
cpu MHz		: 1000.000
cache size	: 4096 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 2
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips	: 2995.39
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:

processor	: 1
vendor_id	: GenuineIntel
cpu family	: 6
model		: 15
model name	: Intel(R) Core(TM)2 CPU         L7400  @ 1.50GHz
stepping	: 6
cpu MHz		: 1000.000
cache size	: 4096 KB
physical id	: 0
siblings	: 2
core id		: 1
cpu cores	: 2
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips	: 2992.46
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:
Comment 1 Roland Scheidegger 2008-02-08 05:34:55 UTC

*** This bug has been marked as a duplicate of bug 8724 ***


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