View All Attachments for Bug 60879

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Attachment #74857
Screenshot of Xorg	image/jpeg	2013-02-15 08:51:22 UTC	1.76 MB	no flags	Details

Attachment #74859
Kernel log when starting Xorg (lines containing radeon or drm)	text/plain	2013-02-15 08:52:19 UTC	8.11 KB	no flags	Details

Attachment #74860
Kernel log when starting weston (lines containing radeon or drm)	text/plain	2013-02-15 08:53:01 UTC	5.71 KB	no flags	Details

Attachment #75409
Debug output	text/plain	2013-02-23 14:36:49 UTC	52.49 KB	no flags	Details

Attachment #76481
Mesa test patch	patch	2013-03-13 15:20:45 UTC	770 bytes	no flags	Details

Attachment #76921
Screenshots with and without glamor	application/x-tar	2013-03-22 21:16:34 UTC	1.61 MB	no flags	Details

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Attachment #77211
Outputs of avivotool	application/x-xz	2013-03-29 14:27:01 UTC	6.82 KB	no flags	Details

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Attachment #79504
Results of OpenCL test	application/x-xz	2013-05-18 19:31:20 UTC	2.38 KB	no flags	Details

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Attachment #88014
Xorg.log	text/plain	2013-10-22 18:18:44 UTC	45.59 KB	no flags	Details

Attachment #98320
/var/log/Xorg.0.log	text/plain	2014-05-02 00:30:30 UTC	84.02 KB	no flags	Details

Attachment #98377
/var/log/Xorg.0.log	text/plain	2014-05-03 12:01:08 UTC	84.12 KB	no flags	Details

Attachment #106530
Fix v5	patch	2014-09-19 01:21:29 UTC	8.62 KB	no flags	Details

Attachment #107322
startx out with -verbose 9, fix v5 + printf's	text/plain	2014-10-04 13:37:39 UTC	33.91 KB	no flags	Details

Attachment #107323
kernel log with tahiti-fix after starting and killing Xorg.bin	text/plain	2014-10-04 13:42:35 UTC	65.21 KB	no flags	Details

Attachment #108412
glxgears output with "Fix v5" in place on 7730 LE	text/plain	2014-10-25 18:39:52 UTC	312 bytes	no flags	Details

Attachment #119959
Tahiti fix v2	patch	2015-11-20 01:14:00 UTC	1.40 KB	no flags	Details

Attachment #119985
v2 patch dmesg	text/plain	2015-11-20 14:55:55 UTC	81.99 KB	no flags	Details

Attachment #120010
dmesg.log with kernel 4.2 with Tahiti fix v2 patch	text/plain	2015-11-22 00:44:52 UTC	91.99 KB	no flags	Details

Attachment #120011
Xorg.0.log with kernel 4.2 with Tahiti fix v2 patch	text/plain	2015-11-22 00:45:21 UTC	39.01 KB	no flags	Details

Attachment #121633
Dmesg Kernel 4.5RC3	text/plain	2016-02-09 20:50:02 UTC	119.98 KB	no flags	Details

Attachment #121634
Xorg.0.log	text/plain	2016-02-09 20:50:30 UTC	50.46 KB	no flags	Details

Attachment #122201
attachment-32429-0.html	text/html	2016-03-10 10:41:18 UTC	2.87 KB	no flags	Details

<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<body>
<p dir="ltr">Thanks for the great explanation, Marek. I will try to start tests today but probably I won't have enough time until weekend.
<br>
</p>
<br>
<br>
<br>
<div class="gmail_quote">On Thu, Mar 10, 2016 at 2:01 AM -0800, <span dir="ltr">&lt;<a href="mailto:bugzilla-daemon@freedesktop.org" target="_blank">bugzilla-daemon@freedesktop.org</a>&gt;</span> wrote:<br>
<br>
</div>
<base href="https://bugs.freedesktop.org/">
<div>
<p></p>
<div><b><a class="x_bz_bug_link x_bz_status_REOPENED" title="REOPENED - [radeonsi] X11 can't start with acceleration enabled" href="https://bugs.freedesktop.org/show_bug.cgi?id=60879#c138">Comment # 138</a> on
<a class="x_bz_bug_link x_bz_status_REOPENED" title="REOPENED - [radeonsi] X11 can't start with acceleration enabled" href="https://bugs.freedesktop.org/show_bug.cgi?id=60879">
bug 60879</a> from <span class="x_vcard"><a class="x_email" href="mailto:maraeo@gmail.com" title="Marek OlÃÂ¡ÃÂ¡k &lt;maraeo@gmail.com&gt;"><span class="x_fn">Marek OlÃÂ¡ÃÂ¡k</span></a>
</span></b>
<pre>I don't think we should use X if we know that the GPU driver is totally broken.
Piglit should be used for such testing.

How to build it:

1) Mesa should be built with:
--with-egl-platforms=x11,drm
This is also required for X acceleration, so it should be set already.

2) Build and install waffle:
git://github.com/waffle-gl/waffle

3) Build piglit (no install):
<a href="https://cgit.freedesktop.org/piglit/">https://cgit.freedesktop.org/piglit/</a>
Configure it with ccmake and enable waffle.


How to get ready:
1) Boot with the &quot;text&quot; kernel parameter (disables X) and also add
&quot;radeon.lockup_timeout=0&quot; to prevent the kernel driver from trying to recover
from GPU hangs.
2) Go to the piglit/bin directory.
3) Type: export PIGLIT_PLATFORM=gbm


Tests to run:

1) If this works, most things will work:
./fbo-generatemipmap-formats -auto

2) Something simpler:
./ext_transform_feedback-position -auto

3) You can invoke very simple internal driver tests by setting GALLIUM_TESTS=1.
This will exit before the program can do something, so the executable doesn't
matter. For example:
GALLIUM_TESTS=1 ./ext_transform_feedback-position


Diagnosing GPU hangs:

If the GPU hangs during these tests, you can see errors in dmesg. I recommend
using radeontop for overview of which GPU hw blocks are busy. If some blocks
report 100% activity for no reason, they are stuck.

Which blocks are stuck is the first piece of information we need to know. Then,
we need to know if any internal driver tests pass if you run something with
GALLIUM_TESTS=1 (see above).</pre>
</div>
<p></p>
<hr>
<span>You are receiving this mail because:</span>
<ul>
<li>You are on the CC list for the bug. </li></ul>
</div>
</body>
</html>

Attachment #122212
Mesa debug file after tests with Marek on the IRC	text/html	2016-03-10 21:26:31 UTC	78.90 KB	no flags	Details

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<!-- This file was created with the aha Ansi HTML Adapter. http://ziz.delphigl.com/tool_aha.php -->
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="application/xml+xhtml; charset=UTF-8" />
<title>wflinfo_931_00000000</title>
</head>
<body style="color:white; background-color:black">
<pre>
Driver vendor: X.Org
Device vendor: AMD
Device name: AMD TAHITI (DRM 2.43.0, LLVM 3.7.1)

<span style="color:yellow;font-weight:bold;">draw_info: </span>{indexed = 0, mode = quads, start = 0, count = 4, start_instance = 0, instance_count = 1, vertices_per_patch = 0, index_bias = 0, min_index = 0, max_index = 3, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, }

<span style="color:yellow;font-weight:bold;">vertex_buffer 0: </span>{stride = 32, buffer_offset = 0, buffer = 0x0078cf60, user_buffer = NULL, }
  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1048576, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 3, bind = 16, flags = 3, }
<span style="color:yellow;font-weight:bold;">num vertex elements</span> = 2
  <span style="color:yellow;font-weight:bold;">vertex_element 0: </span>{src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
  <span style="color:yellow;font-weight:bold;">vertex_element 1: </span>{src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
<span style="color:yellow;font-weight:bold;">num stream output targets</span> = 0

<span style="color:lime;font-weight:bold;">begin shader: VERTEX</span>
<span style="color:yellow;font-weight:bold;">shader_state: </span>{tokens = &quot;
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
&quot;, }
<span style="color:lime;font-weight:bold;">end shader: VERTEX</span>

<span style="color:yellow;font-weight:bold;">viewport_state 0: </span>{scale = {128, 128, 1, }, translate = {128, 128, 0, }, }
<span style="color:yellow;font-weight:bold;">rasterizer_state: </span>{flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 0, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 0, point_quad_rasterization = 0, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 0, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 0, bottom_edge_rule = 0, rasterizer_discard = 1, depth_clip = 0, clip_halfz = 0, clip_plane_enable = 0, line_width = 0, point_size = 0, offset_units = 0, offset_scale = 0, offset_clamp = 0, }

<span style="color:yellow;font-weight:bold;">depth_stencil_alpha_state: </span>{depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, }
<span style="color:yellow;font-weight:bold;">stencil_ref: </span>{ref_value = {0, 0, }, }
<span style="color:yellow;font-weight:bold;">blend_state: </span>{dither = 0, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, }
<span style="color:yellow;font-weight:bold;">blend_color: </span>{color = {0, 0, 0, 0, }, }
<span style="color:yellow;font-weight:bold;">min_samples</span> = 0
<span style="color:yellow;font-weight:bold;">sample_mask</span> = 0xffffffff

<span style="color:yellow;font-weight:bold;">framebuffer_state: </span>{width = 256, height = 256, nr_cbufs = 1, cbufs = {0x00788ea0, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, }
  <span style="color:yellow;font-weight:bold;">cbufs[0]:</span>
    <span style="color:yellow;font-weight:bold;">surface: </span>{format = PIPE_FORMAT_R8G8B8A8_UNORM, width = 256, height = 256, texture = 0x00787df0, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
    <span style="color:yellow;font-weight:bold;">resource: </span>{target = 2d, format = PIPE_FORMAT_R8G8B8A8_UNORM, width0 = 256, height0 = 256, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 10, flags = 0, }



*****************************************************************************
Driver-specific state:

Memory-mapped registers:
        <span style="color:yellow;font-weight:bold;">GRBM_STATUS</span> &lt;- ME0PIPE0_CMDFIFO_AVAIL = 8
                       SRBM_RQ_PENDING = 1
                       ME0PIPE0_CF_RQ_PENDING = 0
                       ME0PIPE0_PF_RQ_PENDING = 0
                       GDS_DMA_RQ_PENDING = 0
                       DB_CLEAN = 1
                       CB_CLEAN = 1
                       TA_BUSY = 0
                       GDS_BUSY = 0
                       WD_BUSY_NO_DMA = 0
                       VGT_BUSY = 1
                       IA_BUSY_NO_DMA = 0
                       IA_BUSY = 0
                       SX_BUSY = 1
                       WD_BUSY = 0
                       SPI_BUSY = 1
                       BCI_BUSY = 0
                       SC_BUSY = 1
                       PA_BUSY = 1
                       DB_BUSY = 0
                       CP_COHERENCY_BUSY = 0
                       CP_BUSY = 1
                       CB_BUSY = 0
                       GUI_ACTIVE = 1

Vertex shader disassembly:
SHADER KEY
  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  as_es = 0
  as_ls = 0
  export_prim_id = 0
	s_load_dwordx4 s[0:3], s[8:9], 0x0                  ; C0800900
	s_load_dwordx4 s[4:7], s[8:9], 0x4                  ; C0820904
	v_add_i32_e32 v0, s10, v0                           ; 4A00000A
	s_waitcnt lgkmcnt(0)                                ; BF8C007F
	buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100
	buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500
	s_waitcnt vmcnt(0)                                  ; BF8C0770
	exp 15, 32, 0, 0, 0, v5, v6, v7, v8                 ; F800020F 08070605
	exp 15, 12, 0, 1, 0, v1, v2, v3, v4                 ; F80008CF 04030201
	s_endpgm                                            ; BF810000


Buffer list (in units of pages = 4kB):
<span style="color:yellow;font-weight:bold;">        Size    VM start page         VM end page           Usage</span>
          16    0x0000000000810       0x0000000000820       BORDER_COLORS
           2    -- hole --
           1    0x0000000000822       0x0000000000823       TRACE
           1    0x0000000000823       0x0000000000824       CMASK
           1    -- hole --
           1    0x0000000000825       0x0000000000826       QUERY
           1    0x0000000000826       0x0000000000827       USER_SHADER
           1    -- hole --
          64    0x0000000000828       0x0000000000868       COLOR_BUFFER
         256    0x0000000000868       0x0000000000968       CONST_BUFFER, DESCRIPTORS
         256    0x0000000000968       0x0000000000a68       VERTEX_BUFFER

Note: The holes represent memory not used by the IB.
      Other buffers can still be allocated there.

------------------ IB begin ------------------
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00822000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000001
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 1
        This trace point was reached by the CP.</span>
<span style="color:lime;font-weight:bold;">CONTEXT_CONTROL</span>:
        0x80000000
        0x80000000
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_HOS_MAX_TESS_LEVEL</span> &lt;- 64.0f
        <span style="color:yellow;font-weight:bold;">VGT_HOS_MIN_TESS_LEVEL</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_PER_ES</span> &lt;- GS_PER_ES = 128
        <span style="color:yellow;font-weight:bold;">VGT_ES_PER_GS</span> &lt;- ES_PER_GS = 64
        <span style="color:yellow;font-weight:bold;">VGT_GS_PER_VS</span> &lt;- GS_PER_VS = 2
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_RESET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_DRAW_OPAQUE_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_REUSE_OFF</span> &lt;- REUSE_OFF = 0
        <span style="color:yellow;font-weight:bold;">VGT_VTX_CNT_EN</span> &lt;- VTX_CNT_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_ENHANCE</span> &lt;- CLIP_VTX_REORDER_ENA = 1
                         NUM_CLIP_SEQ = 3
                         CLIPPED_PRIM_SEQ_STALL = 0
                         VE_NAN_PROC_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_0</span> &lt;- DISTANCE_0 = 0
                                     DISTANCE_1 = 1
                                     DISTANCE_2 = 2
                                     DISTANCE_3 = 3
                                     DISTANCE_4 = 4
                                     DISTANCE_5 = 5
                                     DISTANCE_6 = 6
                                     DISTANCE_7 = 7
        <span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_1</span> &lt;- DISTANCE_8 = 8
                                     DISTANCE_9 = 9
                                     DISTANCE_10 = 10
                                     DISTANCE_11 = 11
                                     DISTANCE_12 = 12
                                     DISTANCE_13 = 13
                                     DISTANCE_14 = 14
                                     DISTANCE_15 = 15
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_PRIM_FILTER_CNTL</span> &lt;- TRIANGLE_FILTER_DISABLE = 0
                                  LINE_FILTER_DISABLE = 0
                                  POINT_FILTER_DISABLE = 0
                                  RECTANGLE_FILTER_DISABLE = 0
                                  TRIANGLE_EXPAND_ENA = 0
                                  LINE_EXPAND_ENA = 0
                                  POINT_EXPAND_ENA = 0
                                  RECTANGLE_EXPAND_ENA = 0
                                  PRIM_EXPAND_CONSTANT = 0
                                  XMAX_RIGHT_EXCLUSION = 0
                                  YMAX_BOTTOM_EXCLUSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_0</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_0</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_1</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_1</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_2</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_3</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_3</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_4</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_4</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_5</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_5</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_6</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_6</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_7</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_7</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_8</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_8</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_9</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_9</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_10</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_10</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_11</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_11</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_12</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_12</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_13</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_13</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_14</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_14</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_15</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_15</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_SC_RASTER_CONFIG</span> &lt;- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_2
                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_2
                               RB_XSEL = 1
                               RB_YSEL = 0
                               PKR_MAP = RASTER_CONFIG_PKR_MAP_2
                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_1
                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
                               SC_MAP = RASTER_CONFIG_SC_MAP_0
                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
                               SE_MAP = RASTER_CONFIG_SE_MAP_2
                               SE_XSEL = RASTER_CONFIG_SE_XSEL_32_WIDE_TILE
                               SE_YSEL = RASTER_CONFIG_SE_YSEL_32_WIDE_TILE
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
                                   WINDOW_OFFSET_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_BR</span> &lt;- BR_X = 16384
                                    BR_Y = 16384
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_BR</span> &lt;- BR_X = 16384
                                   BR_Y = 16384
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CLIPRECT_RULE</span> &lt;- CLIP_RULE = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_EDGERULE</span> &lt;- ER_TRI = 10
                          ER_POINT = 10
                          ER_RECT = 10
                          ER_LINE_LR = 42
                          ER_LINE_RL = 42
                          ER_LINE_TB = 10
                          ER_LINE_BT = 10
        <span style="color:yellow;font-weight:bold;">PA_SU_HARDWARE_SCREEN_OFFSET</span> &lt;- HW_SCREEN_OFFSET_X = 0
                                        HW_SCREEN_OFFSET_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_NANINF_CNTL</span> &lt;- VTE_XY_INF_DISCARD = 0
                             VTE_Z_INF_DISCARD = 0
                             VTE_W_INF_DISCARD = 0
                             VTE_0XNANINF_IS_0 = 0
                             VTE_XY_NAN_RETAIN = 0
                             VTE_Z_NAN_RETAIN = 0
                             VTE_W_NAN_RETAIN = 0
                             VTE_W_RECIP_NAN_IS_0 = 0
                             VS_XY_NAN_TO_INF = 0
                             VS_XY_INF_RETAIN = 0
                             VS_Z_NAN_TO_INF = 0
                             VS_Z_INF_RETAIN = 0
                             VS_W_NAN_TO_INF = 0
                             VS_W_INF_RETAIN = 0
                             VS_CLIP_DIST_INF_DISCARD = 0
                             VTE_NO_OUTPUT_NEG_0 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_CLIP_ADJ</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_DISC_ADJ</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_CLIP_ADJ</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_DISC_ADJ</span> &lt;- 1.0f
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_STENCIL_CLEAR</span> &lt;- CLEAR = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE0</span> &lt;- COMPAREFUNC0 = REF_NEVER
                                      COMPAREVALUE0 = 0
                                      COMPAREMASK0 = 0
                                      ENABLE0 = 0
        <span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE1</span> &lt;- COMPAREFUNC1 = REF_NEVER
                                      COMPAREVALUE1 = 0
                                      COMPAREMASK1 = 0
                                      ENABLE1 = 0
        <span style="color:yellow;font-weight:bold;">DB_PRELOAD_CONTROL</span> &lt;- START_X = 0
                              START_Y = 0
                              MAX_X = 0
                              MAX_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE</span> &lt;- FORCE_HIZ_ENABLE = FORCE_OFF
                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
                              FORCE_SHADER_Z_ORDER = 0
                              FAST_Z_DISABLE = 0
                              FAST_STENCIL_DISABLE = 1
                              NOOP_CULL_DISABLE = 0
                              FORCE_COLOR_KILL = 0
                              FORCE_Z_READ = 0
                              FORCE_STENCIL_READ = 0
                              FORCE_FULL_Z_RANGE = FORCE_OFF
                              FORCE_QC_SMASK_CONFLICT = 0
                              DISABLE_VIEWPORT_CLAMP = 0
                              IGNORE_SC_ZRANGE = 0
                              DISABLE_FULLY_COVERED = 0
                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
                              MAX_TILES_IN_DTT = 0
                              DISABLE_TILE_RATE_TILES = 0
                              FORCE_Z_DIRTY = 0
                              FORCE_STENCIL_DIRTY = 0
                              FORCE_Z_VALID = 0
                              FORCE_STENCIL_VALID = 0
                              PRESERVE_COMPRESSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MAX_VTX_INDX</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">VGT_MIN_VTX_INDX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">VGT_INDX_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">TA_BC_BASE_ADDR</span> &lt;- 0x00008100
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = SAMPLE_STREAMOUTSTATS
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 3
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">ADDRESS_LO</span> &lt;- 0x00825020
        <span style="color:yellow;font-weight:bold;">ADDRESS_HI</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_CB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_DB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">SURFACE_SYNC</span>:
        <span style="color:yellow;font-weight:bold;">CP_COHER_CNTL</span> &lt;- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 1
                         SH_ICACHE_ACTION_ENA = 1
        <span style="color:yellow;font-weight:bold;">CP_COHER_SIZE</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">CP_COHER_BASE</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">POLL_INTERVAL</span> &lt;- 10
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_CONFIG</span> &lt;- STREAMOUT_0_EN = 1
                              STREAMOUT_1_EN = 1
                              STREAMOUT_2_EN = 1
                              STREAMOUT_3_EN = 1
                              RAST_STREAM = 0
                              RAST_STREAM_MASK = 0
                              USE_RAST_STREAM_MASK = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR0_BASE</span> &lt;- 0x00008280
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_PITCH</span> &lt;- TILE_MAX = 31
                           FMASK_TILE_MAX = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_SLICE</span> &lt;- TILE_MAX = 1023
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_VIEW</span> &lt;- SLICE_START = 0
                          SLICE_MAX = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_ATTRIB</span> &lt;- TILE_MODE_INDEX = 16
                            FMASK_TILE_MODE_INDEX = 16
                            FMASK_BANK_HEIGHT = 0
                            NUM_SAMPLES = 0
                            NUM_FRAGMENTS = 0
                            FORCE_DST_ALPHA_1 = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_DCC_CONTROL</span> &lt;- OVERWRITE_COMBINER_DISABLE = 0
                                 KEY_CLEAR_ENABLE = 0
                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
                                 MIN_COMPRESSED_BLOCK_SIZE = 0
                                 MAX_COMPRESSED_BLOCK_SIZE = 0
                                 COLOR_TRANSFORM = 0
                                 INDEPENDENT_64B_BLOCKS = 0
                                 LOSSY_RGB_PRECISION = 0
                                 LOSSY_ALPHA_PRECISION = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CMASK</span> &lt;- 0x00008230
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CMASK_SLICE</span> &lt;- TILE_MAX = 7
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_FMASK</span> &lt;- 0x00008280
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_FMASK_SLICE</span> &lt;- TILE_MAX = 1023
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CLEAR_WORD0</span> &lt;- 0x1a1a1a1a
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CLEAR_WORD1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR1_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR2_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR3_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR4_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR5_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR6_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR7_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_Z_INFO</span> &lt;- FORMAT = Z_INVALID
                     NUM_SAMPLES = 0
                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                     TILE_MODE_INDEX = 0
                     DECOMPRESS_ON_N_ZPLANES = 0
                     ALLOW_EXPCLEAR = 0
                     READ_SIZE = 0
                     TILE_SURFACE_ENABLE = 0
                     CLEAR_DISALLOWED = 0
                     ZRANGE_PRECISION = 0
        <span style="color:yellow;font-weight:bold;">DB_STENCIL_INFO</span> &lt;- FORMAT = STENCIL_INVALID
                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                           TILE_MODE_INDEX = 0
                           ALLOW_EXPCLEAR = 0
                           TILE_STENCIL_DISABLE = 0
                           CLEAR_DISALLOWED = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_BR</span> &lt;- BR_X = 256
                                   BR_Y = 256
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0</span> &lt;- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0</span> &lt;- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0</span> &lt;- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0</span> &lt;- S0_X = 14
                                             S0_Y = 11
                                             S1_X = 3
                                             S1_Y = 12
                                             S2_X = 15
                                             S2_Y = 5
                                             S3_X = 10
                                             S3_Y = 14
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_CONTROL</span> &lt;- DEPTH_CLEAR_ENABLE = 0
                             STENCIL_CLEAR_ENABLE = 0
                             DEPTH_COPY = 0
                             STENCIL_COPY = 0
                             RESUMMARIZE_ENABLE = 0
                             STENCIL_COMPRESS_DISABLE = 0
                             DEPTH_COMPRESS_DISABLE = 0
                             COPY_CENTROID = 0
                             COPY_SAMPLE = 0
                             DECOMPRESS_ENABLE = 0
        <span style="color:yellow;font-weight:bold;">DB_COUNT_CONTROL</span> &lt;- ZPASS_INCREMENT_DISABLE = 1
                            PERFECT_ZPASS_COUNTS = 0
                            SAMPLE_RATE = 0
                            ZPASS_ENABLE = 0
                            ZFAIL_ENABLE = 0
                            SFAIL_ENABLE = 0
                            DBFAIL_ENABLE = 0
                            SLICE_EVEN_ENABLE = 0
                            SLICE_ODD_ENABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE2</span> &lt;- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_COLOR_ON_VALIDATION = 0
                               DECOMPRESS_Z_ON_FLUSH = 0
                               DISABLE_REG_SNOOP = 0
                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
                               SEPARATE_HIZS_FUNC_ENABLE = 0
                               HIZ_ZFUNC = 0
                               HIS_SFUNC_FF = 0
                               HIS_SFUNC_BF = 0
                               PRESERVE_ZRANGE = 0
                               PRESERVE_SRESULTS = 0
                               DISABLE_FAST_PASS = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SHADER_CONTROL</span> &lt;- Z_EXPORT_ENABLE = 0
                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
                             Z_ORDER = EARLY_Z_THEN_LATE_Z
                             KILL_ENABLE = 0
                             COVERAGE_TO_MASK_ENABLE = 0
                             MASK_EXPORT_ENABLE = 0
                             EXEC_ON_HIER_FAIL = 0
                             EXEC_ON_NOOP = 0
                             ALPHA_TO_MASK_DISABLE = 0
                             DEPTH_BEFORE_SHADER = 0
                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
                             DUAL_QUAD_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_LINE_CNTL</span> &lt;- EXPAND_LINE_WIDTH = 0
                           LAST_PIXEL = 1
                           PERPENDICULAR_ENDCAP_ENA = 0
                           DX10_DIAMOND_TEST_ENA = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_CONFIG</span> &lt;- MSAA_NUM_SAMPLES = 0
                           AA_MASK_CENTROID_DTMN = 0
                           MAX_SAMPLE_DIST = 0
                           MSAA_EXPOSED_SAMPLES = 0
                           DETAIL_TO_EXPOSED_MODE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_EQAA</span> &lt;- MAX_ANCHOR_SAMPLES = 0
                   PS_ITER_SAMPLES = 0
                   MASK_EXPORT_NUM_SAMPLES = 0
                   ALPHA_TO_MASK_NUM_SAMPLES = 0
                   HIGH_QUALITY_INTERSECTIONS = 1
                   INCOHERENT_EQAA_READS = 0
                   INTERPOLATE_COMP_Z = 0
                   INTERPOLATE_SRC_Z = 0
                   STATIC_ANCHOR_ASSOCIATIONS = 1
                   ALPHA_TO_MASK_EQAA_DISABLE = 0
                   OVERRASTERIZATION_AMOUNT = 0
                   ENABLE_POSTZ_OVERRASTERIZATION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_MODE_CNTL_1</span> &lt;- WALK_SIZE = 0
                             WALK_ALIGNMENT = 0
                             WALK_ALIGN8_PRIM_FITS_ST = 0
                             WALK_FENCE_ENABLE = 0
                             WALK_FENCE_SIZE = 0
                             SUPERTILE_WALK_ORDER_ENABLE = 0
                             TILE_WALK_ORDER_ENABLE = 0
                             TILE_COVER_DISABLE = 0
                             TILE_COVER_NO_SCISSOR = 0
                             ZMM_LINE_EXTENT = 0
                             ZMM_LINE_OFFSET = 0
                             ZMM_RECT_EXTENT = 0
                             KILL_PIX_POST_HI_Z = 0
                             KILL_PIX_POST_DETAIL_MASK = 0
                             PS_ITER_SAMPLE = 0
                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
                             MULTI_GPU_SUPERTILE_ENABLE = 0
                             GPU_ID_OVERRIDE_ENABLE = 0
                             GPU_ID_OVERRIDE = 0
                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
                             FORCE_EOV_CNTDWN_ENABLE = 1
                             FORCE_EOV_REZ_ENABLE = 1
                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
                             OUT_OF_ORDER_WATER_MARK = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_AA_MASK_X0Y0_X1Y0</span> &lt;- AA_MASK_X0Y0 = 0xffff
                                   AA_MASK_X1Y0 = 0xffff
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_MASK_X0Y1_X1Y1</span> &lt;- AA_MASK_X0Y1 = 0xffff
                                   AA_MASK_X1Y1 = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_TARGET_MASK</span> &lt;- TARGET0_ENABLE = 15
                          TARGET1_ENABLE = 0
                          TARGET2_ENABLE = 0
                          TARGET3_ENABLE = 0
                          TARGET4_ENABLE = 0
                          TARGET5_ENABLE = 0
                          TARGET6_ENABLE = 0
                          TARGET7_ENABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_BLEND_RED</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_GREEN</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_BLUE</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_ALPHA</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VS_OUT_CNTL</span> &lt;- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_CLIP_CNTL</span> &lt;- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 1
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 1
                           ZCLIP_FAR_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_W</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_0</span> &lt;- 0x00868300
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_2</span> &lt;- 0x00868100
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_6</span> &lt;- 0x00868400
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_4</span> &lt;- 0x00868900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_0</span> &lt;- 0x00868d00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_2</span> &lt;- 0x00868b00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_6</span> &lt;- 0x00868e00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_4</span> &lt;- 0x00869300
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_0</span> &lt;- 0x00869700
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_2</span> &lt;- 0x00869500
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_6</span> &lt;- 0x00869800
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_4</span> &lt;- 0x00869d00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_0</span> &lt;- 0x0086a100
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_2</span> &lt;- 0x00869f00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_6</span> &lt;- 0x0086a200
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_4</span> &lt;- 0x0086a700
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_8</span> &lt;- 0x0086b300
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_9</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_SCISSOR_0_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_SCISSOR_0_BR</span> &lt;- BR_X = 0
                                    BR_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VPORT_XSCALE</span> &lt;- 128.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_XOFFSET</span> &lt;- 128.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_YSCALE</span> &lt;- 128.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_YOFFSET</span> &lt;- 128.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_ZSCALE</span> &lt;- 1.0f
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_ZOFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_STENCILREFMASK</span> &lt;- STENCILTESTVAL = 0
                             STENCILMASK = 0
                             STENCILWRITEMASK = 0
                             STENCILOPVAL = 1
        <span style="color:yellow;font-weight:bold;">DB_STENCILREFMASK_BF</span> &lt;- STENCILTESTVAL_BF = 0
                                STENCILMASK_BF = 0
                                STENCILWRITEMASK_BF = 0
                                STENCILOPVAL_BF = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_ALPHA_TO_MASK</span> &lt;- ALPHA_TO_MASK_ENABLE = 0
                            ALPHA_TO_MASK_OFFSET0 = 2
                            ALPHA_TO_MASK_OFFSET1 = 2
                            ALPHA_TO_MASK_OFFSET2 = 2
                            ALPHA_TO_MASK_OFFSET3 = 2
                            OFFSET_ROUND = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_BLEND0_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND1_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND2_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND3_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND4_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND5_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND6_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND7_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR_CONTROL</span> &lt;- DEGAMMA_ENABLE = 0
                            MODE = CB_NORMAL
                            ROP3 = X_0XCC
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_INTERP_CONTROL_0</span> &lt;- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_POINT_SIZE</span> &lt;- HEIGHT = 0
                            WIDTH = 0
        <span style="color:yellow;font-weight:bold;">PA_SU_POINT_MINMAX</span> &lt;- MIN_SIZE = 0
                              MAX_SIZE = 0
        <span style="color:yellow;font-weight:bold;">PA_SU_LINE_CNTL</span> &lt;- WIDTH = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_MODE_CNTL_0</span> &lt;- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_VTX_CNTL</span> &lt;- PIX_CENTER = 0
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_POLY_OFFSET_CLAMP</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_SC_MODE_CNTL</span> &lt;- CULL_FRONT = 0
                              CULL_BACK = 0
                              FACE = 1
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_12</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_DEPTH_CONTROL</span> &lt;- STENCIL_ENABLE = 0
                            Z_ENABLE = 0
                            Z_WRITE_ENABLE = 0
                            DEPTH_BOUNDS_ENABLE = 0
                            ZFUNC = FRAG_NEVER
                            BACKFACE_ENABLE = 0
                            STENCILFUNC = REF_NEVER
                            STENCILFUNC_BF = REF_NEVER
                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_STENCIL_CONTROL</span> &lt;- STENCILFAIL = STENCIL_KEEP
                              STENCILZPASS = STENCIL_KEEP
                              STENCILZFAIL = STENCIL_KEEP
                              STENCILFAIL_BF = STENCIL_KEEP
                              STENCILZPASS_BF = STENCIL_KEEP
                              STENCILZFAIL_BF = STENCIL_KEEP
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_SHADER_STAGES_EN</span> &lt;- LS_EN = LS_STAGE_OFF
                                HS_EN = 0
                                ES_EN = ES_STAGE_OFF
                                GS_EN = 0
                                VS_EN = VS_STAGE_REAL
                                DYNAMIC_HS = 0
                                DISPATCH_DRAW_EN = 0
                                DIS_DEALLOC_ACCUM_0 = 0
                                DIS_DEALLOC_ACCUM_1 = 0
                                VS_WAVE_ID_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_MODE</span> &lt;- MODE = GS_OFF
                       RESERVED_0 = 0
                       CUT_MODE = GS_CUT_1024
                       RESERVED_1 = 0
                       GS_C_PACK_EN = 0
                       RESERVED_2 = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_EN</span> &lt;- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_VS_OUT_CONFIG</span> &lt;- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_POS_FORMAT</span> &lt;- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_LO_VS</span> &lt;- 0x00008260
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_HI_VS</span> &lt;- MEM_BASE = 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_RSRC1_VS</span> &lt;- VGPRS = 2
                                   SGPRS = 1
                                   PRIORITY = 0
                                   FLOAT_MODE = 0
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_RSRC2_VS</span> &lt;- SCRATCH_EN = 0
                                   USER_SGPR = 13
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VTE_CNTL</span> &lt;- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_TMPRING_SIZE</span> &lt;- WAVES = 768
                            WAVESIZE = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVE_TYPE</span> &lt;- PRIM_TYPE = DI_PT_QUADLIST
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">IA_MULTI_VGT_PARAM</span> &lt;- PRIMGROUP_SIZE = 127
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_LS_HS_CONFIG</span> &lt;- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_OUT_PRIM_TYPE</span> &lt;- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
                                OUTPRIM_TYPE_1 = 0
                                OUTPRIM_TYPE_2 = 0
                                OUTPRIM_TYPE_3 = 0
                                UNIQUE_TYPE_PER_STREAM = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MULTI_PRIM_IB_RESET_EN</span> &lt;- RESET_EN = 0
<span style="color:lime;font-weight:bold;">NUM_INSTANCES</span>:
        <span style="color:yellow;font-weight:bold;">VGT_NUM_INSTANCES</span> &lt;- 1
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_10</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_11</span> &lt;- 0
<span style="color:lime;font-weight:bold;">DRAW_INDEX_AUTO</span>:
        <span style="color:yellow;font-weight:bold;">VGT_NUM_INDICES</span> &lt;- 4
        <span style="color:yellow;font-weight:bold;">VGT_DRAW_INITIATOR</span> &lt;- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00822000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000002
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 2
        !!!!! This is the last trace point that was reached by the CP !!!!!</span>
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = SAMPLE_STREAMOUTSTATS
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 3
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">ADDRESS_LO</span> &lt;- 0x00825030
        <span style="color:yellow;font-weight:bold;">ADDRESS_HI</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_CB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_DB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = PS_PARTIAL_FLUSH
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 4
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">SURFACE_SYNC</span>:
        <span style="color:yellow;font-weight:bold;">CP_COHER_CNTL</span> &lt;- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 0
        <span style="color:yellow;font-weight:bold;">CP_COHER_SIZE</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">CP_COHER_BASE</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">POLL_INTERVAL</span> &lt;- 10
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00822000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000003
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 3
        !!!!! This trace point was NOT reached by the CP !!!!!</span>
------------------- IB end -------------------
Done.
</pre>
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Attachment #122225
possible fix	patch	2016-03-11 14:04:01 UTC	2.38 KB	no flags	Details

Attachment #122240
Dump with Marek patch	text/html	2016-03-11 21:38:39 UTC	93.01 KB	no flags	Details

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<!-- This file was created with the aha Ansi HTML Adapter. http://ziz.delphigl.com/tool_aha.php -->
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="application/xml+xhtml; charset=UTF-8" />
<title>wflinfo_2328_00000000</title>
</head>
<body style="color:white; background-color:black">
<pre>
Driver vendor: X.Org
Device vendor: AMD
Device name: AMD TAHITI (DRM 2.43.0, LLVM 3.7.1)

<span style="color:yellow;font-weight:bold;">draw_info: </span>{indexed = 0, mode = quads, start = 0, count = 4, start_instance = 0, instance_count = 1, vertices_per_patch = 0, index_bias = 0, min_index = 0, max_index = 3, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, }

<span style="color:yellow;font-weight:bold;">vertex_buffer 0: </span>{stride = 32, buffer_offset = 0, buffer = 0x021c3b50, user_buffer = NULL, }
  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1048576, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 3, bind = 16, flags = 3, }
<span style="color:yellow;font-weight:bold;">num vertex elements</span> = 2
  <span style="color:yellow;font-weight:bold;">vertex_element 0: </span>{src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
  <span style="color:yellow;font-weight:bold;">vertex_element 1: </span>{src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
<span style="color:yellow;font-weight:bold;">num stream output targets</span> = 0

<span style="color:lime;font-weight:bold;">begin shader: VERTEX</span>
<span style="color:yellow;font-weight:bold;">shader_state: </span>{tokens = &quot;
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
&quot;, }
<span style="color:lime;font-weight:bold;">end shader: VERTEX</span>

<span style="color:yellow;font-weight:bold;">viewport_state 0: </span>{scale = {128, 128, 1, }, translate = {128, 128, 0, }, }
<span style="color:yellow;font-weight:bold;">rasterizer_state: </span>{flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 0, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 0, point_quad_rasterization = 0, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 0, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 0, bottom_edge_rule = 0, rasterizer_discard = 1, depth_clip = 0, clip_halfz = 0, clip_plane_enable = 0, line_width = 0, point_size = 0, offset_units = 0, offset_scale = 0, offset_clamp = 0, }

<span style="color:yellow;font-weight:bold;">depth_stencil_alpha_state: </span>{depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, }
<span style="color:yellow;font-weight:bold;">stencil_ref: </span>{ref_value = {0, 0, }, }
<span style="color:yellow;font-weight:bold;">blend_state: </span>{dither = 0, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, }
<span style="color:yellow;font-weight:bold;">blend_color: </span>{color = {0, 0, 0, 0, }, }
<span style="color:yellow;font-weight:bold;">min_samples</span> = 0
<span style="color:yellow;font-weight:bold;">sample_mask</span> = 0xffffffff

<span style="color:yellow;font-weight:bold;">framebuffer_state: </span>{width = 256, height = 256, nr_cbufs = 1, cbufs = {0x021ae740, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, }
  <span style="color:yellow;font-weight:bold;">cbufs[0]:</span>
    <span style="color:yellow;font-weight:bold;">surface: </span>{format = PIPE_FORMAT_R8G8B8A8_UNORM, width = 256, height = 256, texture = 0x021bed00, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
    <span style="color:yellow;font-weight:bold;">resource: </span>{target = 2d, format = PIPE_FORMAT_R8G8B8A8_UNORM, width0 = 256, height0 = 256, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 10, flags = 0, }



*****************************************************************************
Driver-specific state:

Memory-mapped registers:
        <span style="color:yellow;font-weight:bold;">GRBM_STATUS</span> &lt;- ME0PIPE0_CMDFIFO_AVAIL = 8
                       SRBM_RQ_PENDING = 1
                       ME0PIPE0_CF_RQ_PENDING = 0
                       ME0PIPE0_PF_RQ_PENDING = 0
                       GDS_DMA_RQ_PENDING = 0
                       DB_CLEAN = 1
                       CB_CLEAN = 1
                       TA_BUSY = 0
                       GDS_BUSY = 0
                       WD_BUSY_NO_DMA = 0
                       VGT_BUSY = 1
                       IA_BUSY_NO_DMA = 0
                       IA_BUSY = 0
                       SX_BUSY = 1
                       WD_BUSY = 0
                       SPI_BUSY = 1
                       BCI_BUSY = 0
                       SC_BUSY = 1
                       PA_BUSY = 1
                       DB_BUSY = 0
                       CP_COHERENCY_BUSY = 0
                       CP_BUSY = 1
                       CB_BUSY = 0
                       GUI_ACTIVE = 1

<span style="color:yellow;font-weight:bold;">Color buffer 0:</span>
  Info: npix_x=256, npix_y=256, npix_z=1, blk_w=1, blk_h=1, blk_d=1, array_size=1, last_level=0, bpe=4, nsamples=1, flags=0x100301, r8g8b8a8_unorm
  Layout: size=262144, alignment=32768, bankw=1, bankh=1, nbanks=0, mtilea=1, tilesplit=512, pipeconfig=0, scanout=0
  CMask: offset=0, size=2048, alignment=2048, pitch=512, height=256, xalign=512, yalign=256, slice_tile_max=7
  Level[0]: offset=0, slice_size=262144, npix_x=256, npix_y=256, npix_z=1, nblk_x=256, nblk_y=256, nblk_z=1, pitch_bytes=1024, mode=3

SHADER KEY
  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  as_es = 0
  as_ls = 0
  export_prim_id = 0

Vertex Shader as VS:
Shader main disassembly:
	s_load_dwordx4 s[0:3], s[8:9], 0x0                  ; C0800900
	s_load_dwordx4 s[4:7], s[8:9], 0x4                  ; C0820904
	v_add_i32_e32 v0, s10, v0                           ; 4A00000A
	s_waitcnt lgkmcnt(0)                                ; BF8C007F
	buffer_load_format_xyzw v[1:4], v0, s[0:3], 0 idxen ; E00C2000 80000100
	buffer_load_format_xyzw v[5:8], v0, s[4:7], 0 idxen ; E00C2000 80010500
	s_waitcnt vmcnt(0)                                  ; BF8C0770
	exp 15, 32, 0, 0, 0, v5, v6, v7, v8                 ; F800020F 08070605
	exp 15, 12, 0, 1, 0, v1, v2, v3, v4                 ; F80008CF 04030201
	s_endpgm                                            ; BF810000

*** SHADER STATS ***
SGPRS: 16
VGPRS: 12
Code Size: 56 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
Max Waves: 10
********************
Buffer list (in units of pages = 4kB):
<span style="color:yellow;font-weight:bold;">        Size    VM start page         VM end page           Usage</span>
          16    0x0000000000810       0x0000000000820       BORDER_COLORS
           2    -- hole --
           1    0x0000000000822       0x0000000000823       TRACE
           1    0x0000000000823       0x0000000000824       CMASK
           1    -- hole --
           1    0x0000000000825       0x0000000000826       QUERY
           1    0x0000000000826       0x0000000000827       USER_SHADER
           1    -- hole --
          64    0x0000000000828       0x0000000000868       COLOR_BUFFER
         256    0x0000000000868       0x0000000000968       CONST_BUFFER, DESCRIPTORS
         256    0x0000000000968       0x0000000000a68       VERTEX_BUFFER

Note: The holes represent memory not used by the IB.
      Other buffers can still be allocated there.

------------------ IB2: Init config begin ------------------
<span style="color:lime;font-weight:bold;">CONTEXT_CONTROL</span>:
        0x80000000
        0x80000000
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_HOS_MAX_TESS_LEVEL</span> &lt;- 64.0f (0x42800000)
        <span style="color:yellow;font-weight:bold;">VGT_HOS_MIN_TESS_LEVEL</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_PER_ES</span> &lt;- GS_PER_ES = 128 (0x80)
        <span style="color:yellow;font-weight:bold;">VGT_ES_PER_GS</span> &lt;- ES_PER_GS = 64 (0x40)
        <span style="color:yellow;font-weight:bold;">VGT_GS_PER_VS</span> &lt;- GS_PER_VS = 2
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_RESET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_DRAW_OPAQUE_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_VTX_CNT_EN</span> &lt;- VTX_CNT_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_ENHANCE</span> &lt;- CLIP_VTX_REORDER_ENA = 1
                         NUM_CLIP_SEQ = 3
                         CLIPPED_PRIM_SEQ_STALL = 0
                         VE_NAN_PROC_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_0</span> &lt;- DISTANCE_0 = 0
                                     DISTANCE_1 = 1
                                     DISTANCE_2 = 2
                                     DISTANCE_3 = 3
                                     DISTANCE_4 = 4
                                     DISTANCE_5 = 5
                                     DISTANCE_6 = 6
                                     DISTANCE_7 = 7
        <span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_1</span> &lt;- DISTANCE_8 = 8
                                     DISTANCE_9 = 9
                                     DISTANCE_10 = 10 (0xa)
                                     DISTANCE_11 = 11 (0xb)
                                     DISTANCE_12 = 12 (0xc)
                                     DISTANCE_13 = 13 (0xd)
                                     DISTANCE_14 = 14 (0xe)
                                     DISTANCE_15 = 15 (0xf)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_PRIM_FILTER_CNTL</span> &lt;- TRIANGLE_FILTER_DISABLE = 0
                                  LINE_FILTER_DISABLE = 0
                                  POINT_FILTER_DISABLE = 0
                                  RECTANGLE_FILTER_DISABLE = 0
                                  TRIANGLE_EXPAND_ENA = 0
                                  LINE_EXPAND_ENA = 0
                                  POINT_EXPAND_ENA = 0
                                  RECTANGLE_EXPAND_ENA = 0
                                  PRIM_EXPAND_CONSTANT = 0
                                  XMAX_RIGHT_EXCLUSION = 0
                                  YMAX_BOTTOM_EXCLUSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_0</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_0</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_1</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_1</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_2</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_3</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_3</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_4</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_4</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_5</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_5</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_6</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_6</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_7</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_7</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_8</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_8</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_9</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_9</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_10</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_10</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_11</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_11</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_12</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_12</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_13</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_13</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_14</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_14</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_15</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_15</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_RASTER_CONFIG</span> &lt;- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_2
                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_2
                               RB_XSEL = 1
                               RB_YSEL = 0
                               PKR_MAP = RASTER_CONFIG_PKR_MAP_2
                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_1
                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
                               SC_MAP = RASTER_CONFIG_SC_MAP_0
                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
                               SE_MAP = RASTER_CONFIG_SE_MAP_2
                               SE_XSEL = RASTER_CONFIG_SE_XSEL_32_WIDE_TILE
                               SE_YSEL = RASTER_CONFIG_SE_YSEL_32_WIDE_TILE
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
                                   WINDOW_OFFSET_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                    BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                   BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CLIPRECT_RULE</span> &lt;- CLIP_RULE = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_EDGERULE</span> &lt;- ER_TRI = 10 (0xa)
                          ER_POINT = 10 (0xa)
                          ER_RECT = 10 (0xa)
                          ER_LINE_LR = 42 (0x2a)
                          ER_LINE_RL = 42 (0x2a)
                          ER_LINE_TB = 10 (0xa)
                          ER_LINE_BT = 10 (0xa)
        <span style="color:yellow;font-weight:bold;">PA_SU_HARDWARE_SCREEN_OFFSET</span> &lt;- HW_SCREEN_OFFSET_X = 0
                                        HW_SCREEN_OFFSET_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_NANINF_CNTL</span> &lt;- VTE_XY_INF_DISCARD = 0
                             VTE_Z_INF_DISCARD = 0
                             VTE_W_INF_DISCARD = 0
                             VTE_0XNANINF_IS_0 = 0
                             VTE_XY_NAN_RETAIN = 0
                             VTE_Z_NAN_RETAIN = 0
                             VTE_W_NAN_RETAIN = 0
                             VTE_W_RECIP_NAN_IS_0 = 0
                             VS_XY_NAN_TO_INF = 0
                             VS_XY_INF_RETAIN = 0
                             VS_Z_NAN_TO_INF = 0
                             VS_Z_INF_RETAIN = 0
                             VS_W_NAN_TO_INF = 0
                             VS_W_INF_RETAIN = 0
                             VS_CLIP_DIST_INF_DISCARD = 0
                             VTE_NO_OUTPUT_NEG_0 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_CLIP_ADJ</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_DISC_ADJ</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_CLIP_ADJ</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_DISC_ADJ</span> &lt;- 1.0f (0x3f800000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE0</span> &lt;- COMPAREFUNC0 = REF_NEVER
                                      COMPAREVALUE0 = 0
                                      COMPAREMASK0 = 0
                                      ENABLE0 = 0
        <span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE1</span> &lt;- COMPAREFUNC1 = REF_NEVER
                                      COMPAREVALUE1 = 0
                                      COMPAREMASK1 = 0
                                      ENABLE1 = 0
        <span style="color:yellow;font-weight:bold;">DB_PRELOAD_CONTROL</span> &lt;- START_X = 0
                              START_Y = 0
                              MAX_X = 0
                              MAX_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE</span> &lt;- FORCE_HIZ_ENABLE = FORCE_OFF
                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
                              FORCE_SHADER_Z_ORDER = 0
                              FAST_Z_DISABLE = 0
                              FAST_STENCIL_DISABLE = 0
                              NOOP_CULL_DISABLE = 0
                              FORCE_COLOR_KILL = 0
                              FORCE_Z_READ = 0
                              FORCE_STENCIL_READ = 0
                              FORCE_FULL_Z_RANGE = FORCE_OFF
                              FORCE_QC_SMASK_CONFLICT = 0
                              DISABLE_VIEWPORT_CLAMP = 0
                              IGNORE_SC_ZRANGE = 0
                              DISABLE_FULLY_COVERED = 0
                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
                              MAX_TILES_IN_DTT = 0
                              DISABLE_TILE_RATE_TILES = 0
                              FORCE_Z_DIRTY = 0
                              FORCE_STENCIL_DIRTY = 0
                              FORCE_Z_VALID = 0
                              FORCE_STENCIL_VALID = 0
                              PRESERVE_COMPRESSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MAX_VTX_INDX</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">VGT_MIN_VTX_INDX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">VGT_INDX_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">TA_BC_BASE_ADDR</span> &lt;- 0x00008100
------------------- IB2: Init config end -------------------

------------------ IB begin ------------------
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00822000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000001
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 1
        This trace point was reached by the CP.</span>
<span style="color:lime;font-weight:bold;">CONTEXT_CONTROL</span>:
        0x80000000
        0x80000000
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_HOS_MAX_TESS_LEVEL</span> &lt;- 64.0f (0x42800000)
        <span style="color:yellow;font-weight:bold;">VGT_HOS_MIN_TESS_LEVEL</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_PER_ES</span> &lt;- GS_PER_ES = 128 (0x80)
        <span style="color:yellow;font-weight:bold;">VGT_ES_PER_GS</span> &lt;- ES_PER_GS = 64 (0x40)
        <span style="color:yellow;font-weight:bold;">VGT_GS_PER_VS</span> &lt;- GS_PER_VS = 2
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_RESET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_DRAW_OPAQUE_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_VTX_CNT_EN</span> &lt;- VTX_CNT_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_ENHANCE</span> &lt;- CLIP_VTX_REORDER_ENA = 1
                         NUM_CLIP_SEQ = 3
                         CLIPPED_PRIM_SEQ_STALL = 0
                         VE_NAN_PROC_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_0</span> &lt;- DISTANCE_0 = 0
                                     DISTANCE_1 = 1
                                     DISTANCE_2 = 2
                                     DISTANCE_3 = 3
                                     DISTANCE_4 = 4
                                     DISTANCE_5 = 5
                                     DISTANCE_6 = 6
                                     DISTANCE_7 = 7
        <span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_1</span> &lt;- DISTANCE_8 = 8
                                     DISTANCE_9 = 9
                                     DISTANCE_10 = 10 (0xa)
                                     DISTANCE_11 = 11 (0xb)
                                     DISTANCE_12 = 12 (0xc)
                                     DISTANCE_13 = 13 (0xd)
                                     DISTANCE_14 = 14 (0xe)
                                     DISTANCE_15 = 15 (0xf)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_PRIM_FILTER_CNTL</span> &lt;- TRIANGLE_FILTER_DISABLE = 0
                                  LINE_FILTER_DISABLE = 0
                                  POINT_FILTER_DISABLE = 0
                                  RECTANGLE_FILTER_DISABLE = 0
                                  TRIANGLE_EXPAND_ENA = 0
                                  LINE_EXPAND_ENA = 0
                                  POINT_EXPAND_ENA = 0
                                  RECTANGLE_EXPAND_ENA = 0
                                  PRIM_EXPAND_CONSTANT = 0
                                  XMAX_RIGHT_EXCLUSION = 0
                                  YMAX_BOTTOM_EXCLUSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_0</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_0</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_1</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_1</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_2</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_3</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_3</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_4</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_4</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_5</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_5</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_6</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_6</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_7</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_7</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_8</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_8</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_9</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_9</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_10</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_10</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_11</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_11</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_12</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_12</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_13</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_13</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_14</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_14</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_15</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_15</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_RASTER_CONFIG</span> &lt;- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_2
                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_2
                               RB_XSEL = 1
                               RB_YSEL = 0
                               PKR_MAP = RASTER_CONFIG_PKR_MAP_2
                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_1
                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
                               SC_MAP = RASTER_CONFIG_SC_MAP_0
                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
                               SE_MAP = RASTER_CONFIG_SE_MAP_2
                               SE_XSEL = RASTER_CONFIG_SE_XSEL_32_WIDE_TILE
                               SE_YSEL = RASTER_CONFIG_SE_YSEL_32_WIDE_TILE
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
                                   WINDOW_OFFSET_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                    BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                   BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CLIPRECT_RULE</span> &lt;- CLIP_RULE = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_EDGERULE</span> &lt;- ER_TRI = 10 (0xa)
                          ER_POINT = 10 (0xa)
                          ER_RECT = 10 (0xa)
                          ER_LINE_LR = 42 (0x2a)
                          ER_LINE_RL = 42 (0x2a)
                          ER_LINE_TB = 10 (0xa)
                          ER_LINE_BT = 10 (0xa)
        <span style="color:yellow;font-weight:bold;">PA_SU_HARDWARE_SCREEN_OFFSET</span> &lt;- HW_SCREEN_OFFSET_X = 0
                                        HW_SCREEN_OFFSET_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_NANINF_CNTL</span> &lt;- VTE_XY_INF_DISCARD = 0
                             VTE_Z_INF_DISCARD = 0
                             VTE_W_INF_DISCARD = 0
                             VTE_0XNANINF_IS_0 = 0
                             VTE_XY_NAN_RETAIN = 0
                             VTE_Z_NAN_RETAIN = 0
                             VTE_W_NAN_RETAIN = 0
                             VTE_W_RECIP_NAN_IS_0 = 0
                             VS_XY_NAN_TO_INF = 0
                             VS_XY_INF_RETAIN = 0
                             VS_Z_NAN_TO_INF = 0
                             VS_Z_INF_RETAIN = 0
                             VS_W_NAN_TO_INF = 0
                             VS_W_INF_RETAIN = 0
                             VS_CLIP_DIST_INF_DISCARD = 0
                             VTE_NO_OUTPUT_NEG_0 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_CLIP_ADJ</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_DISC_ADJ</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_CLIP_ADJ</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_DISC_ADJ</span> &lt;- 1.0f (0x3f800000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE0</span> &lt;- COMPAREFUNC0 = REF_NEVER
                                      COMPAREVALUE0 = 0
                                      COMPAREMASK0 = 0
                                      ENABLE0 = 0
        <span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE1</span> &lt;- COMPAREFUNC1 = REF_NEVER
                                      COMPAREVALUE1 = 0
                                      COMPAREMASK1 = 0
                                      ENABLE1 = 0
        <span style="color:yellow;font-weight:bold;">DB_PRELOAD_CONTROL</span> &lt;- START_X = 0
                              START_Y = 0
                              MAX_X = 0
                              MAX_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE</span> &lt;- FORCE_HIZ_ENABLE = FORCE_OFF
                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
                              FORCE_SHADER_Z_ORDER = 0
                              FAST_Z_DISABLE = 0
                              FAST_STENCIL_DISABLE = 0
                              NOOP_CULL_DISABLE = 0
                              FORCE_COLOR_KILL = 0
                              FORCE_Z_READ = 0
                              FORCE_STENCIL_READ = 0
                              FORCE_FULL_Z_RANGE = FORCE_OFF
                              FORCE_QC_SMASK_CONFLICT = 0
                              DISABLE_VIEWPORT_CLAMP = 0
                              IGNORE_SC_ZRANGE = 0
                              DISABLE_FULLY_COVERED = 0
                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
                              MAX_TILES_IN_DTT = 0
                              DISABLE_TILE_RATE_TILES = 0
                              FORCE_Z_DIRTY = 0
                              FORCE_STENCIL_DIRTY = 0
                              FORCE_Z_VALID = 0
                              FORCE_STENCIL_VALID = 0
                              PRESERVE_COMPRESSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MAX_VTX_INDX</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">VGT_MIN_VTX_INDX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">VGT_INDX_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">TA_BC_BASE_ADDR</span> &lt;- 0x00008100
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = SAMPLE_STREAMOUTSTATS
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 3
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">ADDRESS_LO</span> &lt;- 0x00825020
        <span style="color:yellow;font-weight:bold;">ADDRESS_HI</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_CB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_DB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">SURFACE_SYNC</span>:
        <span style="color:yellow;font-weight:bold;">CP_COHER_CNTL</span> &lt;- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 1
                         SH_ICACHE_ACTION_ENA = 1
        <span style="color:yellow;font-weight:bold;">CP_COHER_SIZE</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">CP_COHER_BASE</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">POLL_INTERVAL</span> &lt;- 10 (0x000a)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_CONFIG</span> &lt;- STREAMOUT_0_EN = 1
                              STREAMOUT_1_EN = 1
                              STREAMOUT_2_EN = 1
                              STREAMOUT_3_EN = 1
                              RAST_STREAM = 0
                              RAST_STREAM_MASK = 0
                              USE_RAST_STREAM_MASK = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR0_BASE</span> &lt;- 0x00008280
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_PITCH</span> &lt;- TILE_MAX = 31 (0x1f)
                           FMASK_TILE_MAX = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_SLICE</span> &lt;- TILE_MAX = 1023 (0x003ff)
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_VIEW</span> &lt;- SLICE_START = 0
                          SLICE_MAX = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_ATTRIB</span> &lt;- TILE_MODE_INDEX = 16 (0x10)
                            FMASK_TILE_MODE_INDEX = 16 (0x10)
                            FMASK_BANK_HEIGHT = 0
                            NUM_SAMPLES = 0
                            NUM_FRAGMENTS = 0
                            FORCE_DST_ALPHA_1 = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_DCC_CONTROL</span> &lt;- OVERWRITE_COMBINER_DISABLE = 0
                                 KEY_CLEAR_ENABLE = 0
                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
                                 MIN_COMPRESSED_BLOCK_SIZE = 0
                                 MAX_COMPRESSED_BLOCK_SIZE = 0
                                 COLOR_TRANSFORM = 0
                                 INDEPENDENT_64B_BLOCKS = 0
                                 LOSSY_RGB_PRECISION = 0
                                 LOSSY_ALPHA_PRECISION = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CMASK</span> &lt;- 0x00008230
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CMASK_SLICE</span> &lt;- TILE_MAX = 7
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_FMASK</span> &lt;- 0x00008280
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_FMASK_SLICE</span> &lt;- TILE_MAX = 1023 (0x003ff)
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CLEAR_WORD0</span> &lt;- 0x1a1a1a1a
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CLEAR_WORD1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR1_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR2_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR3_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR4_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR5_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR6_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR7_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_Z_INFO</span> &lt;- FORMAT = Z_INVALID
                     NUM_SAMPLES = 0
                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                     TILE_MODE_INDEX = 0
                     DECOMPRESS_ON_N_ZPLANES = 0
                     ALLOW_EXPCLEAR = 0
                     READ_SIZE = 0
                     TILE_SURFACE_ENABLE = 0
                     CLEAR_DISALLOWED = 0
                     ZRANGE_PRECISION = 0
        <span style="color:yellow;font-weight:bold;">DB_STENCIL_INFO</span> &lt;- FORMAT = STENCIL_INVALID
                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                           TILE_MODE_INDEX = 0
                           ALLOW_EXPCLEAR = 0
                           TILE_STENCIL_DISABLE = 0
                           CLEAR_DISALLOWED = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_BR</span> &lt;- BR_X = 256 (0x100)
                                   BR_Y = 256 (0x100)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0</span> &lt;- S0_X = 14 (0xe)
                                             S0_Y = 11 (0xb)
                                             S1_X = 3
                                             S1_Y = 12 (0xc)
                                             S2_X = 15 (0xf)
                                             S2_Y = 5
                                             S3_X = 10 (0xa)
                                             S3_Y = 14 (0xe)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11 (0xb)
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0</span> &lt;- S0_X = 14 (0xe)
                                             S0_Y = 11 (0xb)
                                             S1_X = 3
                                             S1_Y = 12 (0xc)
                                             S2_X = 15 (0xf)
                                             S2_Y = 5
                                             S3_X = 10 (0xa)
                                             S3_Y = 14 (0xe)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11 (0xb)
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0</span> &lt;- S0_X = 14 (0xe)
                                             S0_Y = 11 (0xb)
                                             S1_X = 3
                                             S1_Y = 12 (0xc)
                                             S2_X = 15 (0xf)
                                             S2_Y = 5
                                             S3_X = 10 (0xa)
                                             S3_Y = 14 (0xe)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11 (0xb)
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0</span> &lt;- S0_X = 14 (0xe)
                                             S0_Y = 11 (0xb)
                                             S1_X = 3
                                             S1_Y = 12 (0xc)
                                             S2_X = 15 (0xf)
                                             S2_Y = 5
                                             S3_X = 10 (0xa)
                                             S3_Y = 14 (0xe)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1</span> &lt;- S4_X = 6
                                             S4_Y = 0
                                             S5_X = 0
                                             S5_Y = 0
                                             S6_X = 11 (0xb)
                                             S6_Y = 3
                                             S7_X = 4
                                             S7_Y = 4
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_CONTROL</span> &lt;- DEPTH_CLEAR_ENABLE = 0
                             STENCIL_CLEAR_ENABLE = 0
                             DEPTH_COPY = 0
                             STENCIL_COPY = 0
                             RESUMMARIZE_ENABLE = 0
                             STENCIL_COMPRESS_DISABLE = 0
                             DEPTH_COMPRESS_DISABLE = 0
                             COPY_CENTROID = 0
                             COPY_SAMPLE = 0
                             DECOMPRESS_ENABLE = 0
        <span style="color:yellow;font-weight:bold;">DB_COUNT_CONTROL</span> &lt;- ZPASS_INCREMENT_DISABLE = 1
                            PERFECT_ZPASS_COUNTS = 0
                            SAMPLE_RATE = 0
                            ZPASS_ENABLE = 0
                            ZFAIL_ENABLE = 0
                            SFAIL_ENABLE = 0
                            DBFAIL_ENABLE = 0
                            SLICE_EVEN_ENABLE = 0
                            SLICE_ODD_ENABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE2</span> &lt;- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_COLOR_ON_VALIDATION = 0
                               DECOMPRESS_Z_ON_FLUSH = 0
                               DISABLE_REG_SNOOP = 0
                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
                               SEPARATE_HIZS_FUNC_ENABLE = 0
                               HIZ_ZFUNC = 0
                               HIS_SFUNC_FF = 0
                               HIS_SFUNC_BF = 0
                               PRESERVE_ZRANGE = 0
                               PRESERVE_SRESULTS = 0
                               DISABLE_FAST_PASS = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SHADER_CONTROL</span> &lt;- Z_EXPORT_ENABLE = 0
                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
                             Z_ORDER = LATE_Z
                             KILL_ENABLE = 0
                             COVERAGE_TO_MASK_ENABLE = 0
                             MASK_EXPORT_ENABLE = 0
                             EXEC_ON_HIER_FAIL = 0
                             EXEC_ON_NOOP = 0
                             ALPHA_TO_MASK_DISABLE = 0
                             DEPTH_BEFORE_SHADER = 0
                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
                             DUAL_QUAD_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_LINE_CNTL</span> &lt;- EXPAND_LINE_WIDTH = 0
                           LAST_PIXEL = 1
                           PERPENDICULAR_ENDCAP_ENA = 0
                           DX10_DIAMOND_TEST_ENA = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_CONFIG</span> &lt;- MSAA_NUM_SAMPLES = 0
                           AA_MASK_CENTROID_DTMN = 0
                           MAX_SAMPLE_DIST = 0
                           MSAA_EXPOSED_SAMPLES = 0
                           DETAIL_TO_EXPOSED_MODE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_EQAA</span> &lt;- MAX_ANCHOR_SAMPLES = 0
                   PS_ITER_SAMPLES = 0
                   MASK_EXPORT_NUM_SAMPLES = 0
                   ALPHA_TO_MASK_NUM_SAMPLES = 0
                   HIGH_QUALITY_INTERSECTIONS = 1
                   INCOHERENT_EQAA_READS = 0
                   INTERPOLATE_COMP_Z = 0
                   INTERPOLATE_SRC_Z = 0
                   STATIC_ANCHOR_ASSOCIATIONS = 1
                   ALPHA_TO_MASK_EQAA_DISABLE = 0
                   OVERRASTERIZATION_AMOUNT = 0
                   ENABLE_POSTZ_OVERRASTERIZATION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_MODE_CNTL_1</span> &lt;- WALK_SIZE = 0
                             WALK_ALIGNMENT = 0
                             WALK_ALIGN8_PRIM_FITS_ST = 0
                             WALK_FENCE_ENABLE = 0
                             WALK_FENCE_SIZE = 0
                             SUPERTILE_WALK_ORDER_ENABLE = 0
                             TILE_WALK_ORDER_ENABLE = 0
                             TILE_COVER_DISABLE = 0
                             TILE_COVER_NO_SCISSOR = 0
                             ZMM_LINE_EXTENT = 0
                             ZMM_LINE_OFFSET = 0
                             ZMM_RECT_EXTENT = 0
                             KILL_PIX_POST_HI_Z = 0
                             KILL_PIX_POST_DETAIL_MASK = 0
                             PS_ITER_SAMPLE = 0
                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
                             MULTI_GPU_SUPERTILE_ENABLE = 0
                             GPU_ID_OVERRIDE_ENABLE = 0
                             GPU_ID_OVERRIDE = 0
                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
                             FORCE_EOV_CNTDWN_ENABLE = 1
                             FORCE_EOV_REZ_ENABLE = 1
                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
                             OUT_OF_ORDER_WATER_MARK = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_AA_MASK_X0Y0_X1Y0</span> &lt;- AA_MASK_X0Y0 = 0xffff
                                   AA_MASK_X1Y0 = 0xffff
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_MASK_X0Y1_X1Y1</span> &lt;- AA_MASK_X0Y1 = 0xffff
                                   AA_MASK_X1Y1 = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_TARGET_MASK</span> &lt;- TARGET0_ENABLE = 15 (0xf)
                          TARGET1_ENABLE = 0
                          TARGET2_ENABLE = 0
                          TARGET3_ENABLE = 0
                          TARGET4_ENABLE = 0
                          TARGET5_ENABLE = 0
                          TARGET6_ENABLE = 0
                          TARGET7_ENABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_BLEND_RED</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_GREEN</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_BLUE</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_ALPHA</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VS_OUT_CNTL</span> &lt;- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_CLIP_CNTL</span> &lt;- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 1
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 1
                           ZCLIP_FAR_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_REUSE_OFF</span> &lt;- REUSE_OFF = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_W</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_0</span> &lt;- 0x00868300
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_2</span> &lt;- 0x00868100
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_4</span> &lt;- 0x00868400
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_0</span> &lt;- 0x00868b00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_2</span> &lt;- 0x00868900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_4</span> &lt;- 0x00868c00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_0</span> &lt;- 0x00869300
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_2</span> &lt;- 0x00869100
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_4</span> &lt;- 0x00869400
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_0</span> &lt;- 0x00869b00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_2</span> &lt;- 0x00869900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_4</span> &lt;- 0x00869c00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_8</span> &lt;- 0x0086a900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_9</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_SCISSOR_0_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_SCISSOR_0_BR</span> &lt;- BR_X = 0
                                    BR_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VPORT_XSCALE</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_XOFFSET</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_YSCALE</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_YOFFSET</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_ZSCALE</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_ZOFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_STENCILREFMASK</span> &lt;- STENCILTESTVAL = 0
                             STENCILMASK = 0
                             STENCILWRITEMASK = 0
                             STENCILOPVAL = 1
        <span style="color:yellow;font-weight:bold;">DB_STENCILREFMASK_BF</span> &lt;- STENCILTESTVAL_BF = 0
                                STENCILMASK_BF = 0
                                STENCILWRITEMASK_BF = 0
                                STENCILOPVAL_BF = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_ALPHA_TO_MASK</span> &lt;- ALPHA_TO_MASK_ENABLE = 0
                            ALPHA_TO_MASK_OFFSET0 = 2
                            ALPHA_TO_MASK_OFFSET1 = 2
                            ALPHA_TO_MASK_OFFSET2 = 2
                            ALPHA_TO_MASK_OFFSET3 = 2
                            OFFSET_ROUND = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_BLEND0_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND1_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND2_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND3_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND4_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND5_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND6_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND7_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR_CONTROL</span> &lt;- DISABLE_DUAL_QUAD = 0
                            DEGAMMA_ENABLE = 0
                            MODE = CB_NORMAL
                            ROP3 = X_0XCC
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_INTERP_CONTROL_0</span> &lt;- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_POINT_SIZE</span> &lt;- HEIGHT = 0
                            WIDTH = 0
        <span style="color:yellow;font-weight:bold;">PA_SU_POINT_MINMAX</span> &lt;- MIN_SIZE = 0
                              MAX_SIZE = 0
        <span style="color:yellow;font-weight:bold;">PA_SU_LINE_CNTL</span> &lt;- WIDTH = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_MODE_CNTL_0</span> &lt;- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 0
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_VTX_CNTL</span> &lt;- PIX_CENTER = 0
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_POLY_OFFSET_CLAMP</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_SC_MODE_CNTL</span> &lt;- CULL_FRONT = 0
                              CULL_BACK = 0
                              FACE = 1
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_12</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_DEPTH_CONTROL</span> &lt;- STENCIL_ENABLE = 0
                            Z_ENABLE = 0
                            Z_WRITE_ENABLE = 0
                            DEPTH_BOUNDS_ENABLE = 0
                            ZFUNC = FRAG_NEVER
                            BACKFACE_ENABLE = 0
                            STENCILFUNC = REF_NEVER
                            STENCILFUNC_BF = REF_NEVER
                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_STENCIL_CONTROL</span> &lt;- STENCILFAIL = STENCIL_KEEP
                              STENCILZPASS = STENCIL_KEEP
                              STENCILZFAIL = STENCIL_KEEP
                              STENCILFAIL_BF = STENCIL_KEEP
                              STENCILZPASS_BF = STENCIL_KEEP
                              STENCILZFAIL_BF = STENCIL_KEEP
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_SHADER_STAGES_EN</span> &lt;- LS_EN = LS_STAGE_OFF
                                HS_EN = 0
                                ES_EN = ES_STAGE_OFF
                                GS_EN = 0
                                VS_EN = VS_STAGE_REAL
                                DYNAMIC_HS = 0
                                DISPATCH_DRAW_EN = 0
                                DIS_DEALLOC_ACCUM_0 = 0
                                DIS_DEALLOC_ACCUM_1 = 0
                                VS_WAVE_ID_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_MODE</span> &lt;- MODE = GS_OFF
                       RESERVED_0 = 0
                       CUT_MODE = GS_CUT_1024
                       RESERVED_1 = 0
                       GS_C_PACK_EN = 0
                       RESERVED_2 = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_EN</span> &lt;- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_VS_OUT_CONFIG</span> &lt;- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_POS_FORMAT</span> &lt;- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_LO_VS</span> &lt;- 0x00008260
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_HI_VS</span> &lt;- MEM_BASE = 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_RSRC1_VS</span> &lt;- VGPRS = 2
                                   SGPRS = 1
                                   PRIORITY = 0
                                   FLOAT_MODE = 192 (0xc0)
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_RSRC2_VS</span> &lt;- SCRATCH_EN = 0
                                   USER_SGPR = 13 (0xd)
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VTE_CNTL</span> &lt;- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_TMPRING_SIZE</span> &lt;- WAVES = 768 (0x300)
                            WAVESIZE = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVE_TYPE</span> &lt;- PRIM_TYPE = DI_PT_QUADLIST
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">IA_MULTI_VGT_PARAM</span> &lt;- PRIMGROUP_SIZE = 127 (0x007f)
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_LS_HS_CONFIG</span> &lt;- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_OUT_PRIM_TYPE</span> &lt;- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
                                OUTPRIM_TYPE_1 = 0
                                OUTPRIM_TYPE_2 = 0
                                OUTPRIM_TYPE_3 = 0
                                UNIQUE_TYPE_PER_STREAM = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MULTI_PRIM_IB_RESET_EN</span> &lt;- RESET_EN = 0
<span style="color:lime;font-weight:bold;">NUM_INSTANCES</span>:
        <span style="color:yellow;font-weight:bold;">VGT_NUM_INSTANCES</span> &lt;- 1
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_10</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_11</span> &lt;- 0
<span style="color:lime;font-weight:bold;">DRAW_INDEX_AUTO</span>:
        <span style="color:yellow;font-weight:bold;">VGT_NUM_INDICES</span> &lt;- 4
        <span style="color:yellow;font-weight:bold;">VGT_DRAW_INITIATOR</span> &lt;- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00822000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000002
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 2
        !!!!! This is the last trace point that was reached by the CP !!!!!</span>
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = SAMPLE_STREAMOUTSTATS
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 3
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">ADDRESS_LO</span> &lt;- 0x00825030
        <span style="color:yellow;font-weight:bold;">ADDRESS_HI</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_CB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = FLUSH_AND_INV_DB_META
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = PS_PARTIAL_FLUSH
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 4
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">SURFACE_SYNC</span>:
        <span style="color:yellow;font-weight:bold;">CP_COHER_CNTL</span> &lt;- DEST_BASE_0_ENA = 0
                         DEST_BASE_1_ENA = 0
                         CB0_DEST_BASE_ENA = 1
                         CB1_DEST_BASE_ENA = 1
                         CB2_DEST_BASE_ENA = 1
                         CB3_DEST_BASE_ENA = 1
                         CB4_DEST_BASE_ENA = 1
                         CB5_DEST_BASE_ENA = 1
                         CB6_DEST_BASE_ENA = 1
                         CB7_DEST_BASE_ENA = 1
                         DB_DEST_BASE_ENA = 1
                         DEST_BASE_2_ENA = 0
                         DEST_BASE_3_ENA = 0
                         TCL1_ACTION_ENA = 1
                         TC_ACTION_ENA = 1
                         CB_ACTION_ENA = 1
                         DB_ACTION_ENA = 1
                         SH_KCACHE_ACTION_ENA = 0
                         SH_ICACHE_ACTION_ENA = 0
        <span style="color:yellow;font-weight:bold;">CP_COHER_SIZE</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">CP_COHER_BASE</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">POLL_INTERVAL</span> &lt;- 10 (0x000a)
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00822000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000003
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 3
        !!!!! This trace point was NOT reached by the CP !!!!!</span>
------------------- IB end -------------------

Done.
</pre>
</body>
</html>

Attachment #122244
Dmesg from the boot I took the debug dump	text/plain	2016-03-11 22:24:23 UTC	62.51 KB	no flags	Details

Attachment #124323
New Mesa dump with Kernel 4.7rc1, mesa-git, llvm-svn	text/html	2016-06-05 02:11:09 UTC	91.87 KB	no flags	Details

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<!-- This file was created with the aha Ansi HTML Adapter. http://ziz.delphigl.com/tool_aha.php -->
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="application/xml+xhtml; charset=UTF-8" />
<title>stdin</title>
</head>
<body style="color:white; background-color:black">
<pre>
Driver vendor: X.Org
Device vendor: AMD
Device name: AMD TAHITI (DRM 2.45.0 / 4.7.0-1-MANJARO, LLVM 3.9.0)

<span style="color:yellow;font-weight:bold;">draw_info: </span>{indexed = 0, mode = quads, start = 0, count = 4, start_instance = 0, instance_count = 1, vertices_per_patch = 0, index_bias = 0, min_index = 0, max_index = 3, primitive_restart = 0, restart_index = 0, count_from_stream_output = NULL, indirect = NULL, indirect_offset = 0, }

<span style="color:yellow;font-weight:bold;">vertex_buffer 0: </span>{stride = 32, buffer_offset = 0, buffer = 0x01425540, user_buffer = NULL, }
  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1048576, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 3, bind = 16, flags = 3, }
<span style="color:yellow;font-weight:bold;">num vertex elements</span> = 2
  <span style="color:yellow;font-weight:bold;">vertex_element 0: </span>{src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
  <span style="color:yellow;font-weight:bold;">vertex_element 1: </span>{src_offset = 16, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32B32A32_FLOAT, }
<span style="color:yellow;font-weight:bold;">num stream output targets</span> = 0

<span style="color:lime;font-weight:bold;">begin shader: VERTEX</span>
<span style="color:yellow;font-weight:bold;">shader_state: </span>{tokens = &quot;
VERT
PROPERTY NEXT_SHADER FRAG
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
&quot;, }
<span style="color:lime;font-weight:bold;">end shader: VERTEX</span>

<span style="color:yellow;font-weight:bold;">viewport_state 0: </span>{scale = {128, 128, 1, }, translate = {128, 128, 0, }, }
<span style="color:yellow;font-weight:bold;">rasterizer_state: </span>{flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 0, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 0, point_quad_rasterization = 0, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 0, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 0, bottom_edge_rule = 0, rasterizer_discard = 1, depth_clip = 0, clip_halfz = 0, clip_plane_enable = 0, line_width = 0, point_size = 0, offset_units = 0, offset_scale = 0, offset_clamp = 0, }

<span style="color:yellow;font-weight:bold;">depth_stencil_alpha_state: </span>{depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, }
<span style="color:yellow;font-weight:bold;">stencil_ref: </span>{ref_value = {0, 0, }, }
<span style="color:yellow;font-weight:bold;">blend_state: </span>{dither = 0, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, }
<span style="color:yellow;font-weight:bold;">blend_color: </span>{color = {0, 0, 0, 0, }, }
<span style="color:yellow;font-weight:bold;">min_samples</span> = 0
<span style="color:yellow;font-weight:bold;">sample_mask</span> = 0xffffffff

<span style="color:yellow;font-weight:bold;">framebuffer_state: </span>{width = 256, height = 256, samples = 0, layers = 0, nr_cbufs = 1, cbufs = {0x013f91a0, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, }
  <span style="color:yellow;font-weight:bold;">cbufs[0]:</span>
    <span style="color:yellow;font-weight:bold;">surface: </span>{format = PIPE_FORMAT_R8G8B8A8_UNORM, width = 256, height = 256, texture = 0x013f80c0, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
    <span style="color:yellow;font-weight:bold;">resource: </span>{target = 2d, format = PIPE_FORMAT_R8G8B8A8_UNORM, width0 = 256, height0 = 256, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 0, bind = 10, flags = 0, }



*****************************************************************************
Driver-specific state:

Memory-mapped registers:
        <span style="color:yellow;font-weight:bold;">GRBM_STATUS</span> &lt;- ME0PIPE0_CMDFIFO_AVAIL = 8
                       SRBM_RQ_PENDING = 1
                       ME0PIPE0_CF_RQ_PENDING = 0
                       ME0PIPE0_PF_RQ_PENDING = 0
                       GDS_DMA_RQ_PENDING = 0
                       DB_CLEAN = 1
                       CB_CLEAN = 1
                       TA_BUSY = 0
                       GDS_BUSY = 0
                       WD_BUSY_NO_DMA = 0
                       VGT_BUSY = 0
                       IA_BUSY_NO_DMA = 0
                       IA_BUSY = 0
                       SX_BUSY = 1
                       WD_BUSY = 0
                       SPI_BUSY = 1
                       BCI_BUSY = 0
                       SC_BUSY = 1
                       PA_BUSY = 1
                       DB_BUSY = 0
                       CP_COHERENCY_BUSY = 0
                       CP_BUSY = 1
                       CB_BUSY = 0
                       GUI_ACTIVE = 1

<span style="color:yellow;font-weight:bold;">Color buffer 0:</span>
  Info: npix_x=256, npix_y=256, npix_z=1, blk_w=1, blk_h=1, blk_d=1, array_size=1, last_level=0, bpe=4, nsamples=1, flags=0x100301, r8g8b8a8_unorm
  Layout: size=262144, alignment=32768, bankw=1, bankh=1, nbanks=0, mtilea=1, tilesplit=512, pipeconfig=0, scanout=0
  CMask: offset=0, size=2048, alignment=2048, pitch=512, height=256, xalign=512, yalign=256, slice_tile_max=7
  Level[0]: offset=0, slice_size=262144, npix_x=256, npix_y=256, npix_z=1, nblk_x=256, nblk_y=256, nblk_z=1, pitch_bytes=1024, mode=3

SHADER KEY
  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  as_es = 0
  as_ls = 0
  export_prim_id = 0

Vertex Shader as VS:
Shader prolog disassembly:
	v_add_i32_e32 v4, vcc, s12, v0 ; 4A08000C
	v_mov_b32_e32 v5, v4           ; 7E0A0304
Shader main disassembly:
	s_load_dwordx4 s[0:3], s[10:11], 0x0                  ; C0800B00
	s_load_dwordx4 s[4:7], s[10:11], 0x4                  ; C0820B04
	s_waitcnt lgkmcnt(0)                                  ; BF8C007F
	buffer_load_format_xyzw v[6:9], v4, s[0:3], 0 idxen   ; E00C2000 80000604
	buffer_load_format_xyzw v[10:13], v5, s[4:7], 0 idxen ; E00C2000 80010A05
	s_waitcnt vmcnt(0)                                    ; BF8C0F70
	exp 15, 32, 0, 0, 0, v10, v11, v12, v13               ; F800020F 0D0C0B0A
	exp 15, 12, 0, 1, 0, v6, v7, v8, v9                   ; F80008CF 09080706
	s_waitcnt expcnt(0)                                   ; BF8C0F0F
Shader epilog disassembly:
	s_endpgm ; BF810000

*** SHADER STATS ***
SGPRS: 17
VGPRS: 16
Code Size: 64 bytes
LDS: 0 blocks
Scratch: 0 bytes per wave
Max Waves: 10
********************
Buffer list (in units of pages = 4kB):
<span style="color:yellow;font-weight:bold;">        Size    VM start page         VM end page           Usage</span>
          16    0x0000000000810       0x0000000000820       BORDER_COLORS
           1    0x0000000000820       0x0000000000821       TRACE
           2    -- hole --
           1    0x0000000000823       0x0000000000824       CMASK
           1    0x0000000000824       0x0000000000825       QUERY
           1    0x0000000000825       0x0000000000826       USER_SHADER
           2    -- hole --
          64    0x0000000000828       0x0000000000868       COLOR_BUFFER
         256    0x0000000000868       0x0000000000968       DESCRIPTORS, RINGS_STREAMOUT
         256    0x0000000000968       0x0000000000a68       VERTEX_BUFFER

Note: The holes represent memory not used by the IB.
      Other buffers can still be allocated there.

------------------ IB2: Init config begin ------------------
<span style="color:lime;font-weight:bold;">CONTEXT_CONTROL</span>:
        0x80000000
        0x80000000
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_HOS_MAX_TESS_LEVEL</span> &lt;- 64.0f (0x42800000)
        <span style="color:yellow;font-weight:bold;">VGT_HOS_MIN_TESS_LEVEL</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_PER_ES</span> &lt;- GS_PER_ES = 128 (0x80)
        <span style="color:yellow;font-weight:bold;">VGT_ES_PER_GS</span> &lt;- ES_PER_GS = 64 (0x40)
        <span style="color:yellow;font-weight:bold;">VGT_GS_PER_VS</span> &lt;- GS_PER_VS = 2
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_RESET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_DRAW_OPAQUE_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_VTX_CNT_EN</span> &lt;- VTX_CNT_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_ENHANCE</span> &lt;- CLIP_VTX_REORDER_ENA = 1
                         NUM_CLIP_SEQ = 3
                         CLIPPED_PRIM_SEQ_STALL = 0
                         VE_NAN_PROC_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_0</span> &lt;- DISTANCE_0 = 0
                                     DISTANCE_1 = 1
                                     DISTANCE_2 = 2
                                     DISTANCE_3 = 3
                                     DISTANCE_4 = 4
                                     DISTANCE_5 = 5
                                     DISTANCE_6 = 6
                                     DISTANCE_7 = 7
        <span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_1</span> &lt;- DISTANCE_8 = 8
                                     DISTANCE_9 = 9
                                     DISTANCE_10 = 10 (0xa)
                                     DISTANCE_11 = 11 (0xb)
                                     DISTANCE_12 = 12 (0xc)
                                     DISTANCE_13 = 13 (0xd)
                                     DISTANCE_14 = 14 (0xe)
                                     DISTANCE_15 = 15 (0xf)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_PRIM_FILTER_CNTL</span> &lt;- TRIANGLE_FILTER_DISABLE = 0
                                  LINE_FILTER_DISABLE = 0
                                  POINT_FILTER_DISABLE = 0
                                  RECTANGLE_FILTER_DISABLE = 0
                                  TRIANGLE_EXPAND_ENA = 0
                                  LINE_EXPAND_ENA = 0
                                  POINT_EXPAND_ENA = 0
                                  RECTANGLE_EXPAND_ENA = 0
                                  PRIM_EXPAND_CONSTANT = 0
                                  XMAX_RIGHT_EXCLUSION = 0
                                  YMAX_BOTTOM_EXCLUSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_0</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_0</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_1</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_1</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_2</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_3</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_3</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_4</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_4</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_5</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_5</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_6</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_6</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_7</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_7</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_8</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_8</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_9</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_9</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_10</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_10</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_11</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_11</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_12</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_12</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_13</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_13</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_14</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_14</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_15</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_15</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_RASTER_CONFIG</span> &lt;- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_2
                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_2
                               RB_XSEL = 1
                               RB_YSEL = 0
                               PKR_MAP = RASTER_CONFIG_PKR_MAP_2
                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_1
                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
                               SC_MAP = RASTER_CONFIG_SC_MAP_0
                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
                               SE_MAP = RASTER_CONFIG_SE_MAP_2
                               SE_XSEL = RASTER_CONFIG_SE_XSEL_32_WIDE_TILE
                               SE_YSEL = RASTER_CONFIG_SE_YSEL_32_WIDE_TILE
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
                                   WINDOW_OFFSET_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                    BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                   BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CLIPRECT_RULE</span> &lt;- CLIP_RULE = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_EDGERULE</span> &lt;- ER_TRI = 10 (0xa)
                          ER_POINT = 10 (0xa)
                          ER_RECT = 10 (0xa)
                          ER_LINE_LR = 42 (0x2a)
                          ER_LINE_RL = 42 (0x2a)
                          ER_LINE_TB = 10 (0xa)
                          ER_LINE_BT = 10 (0xa)
        <span style="color:yellow;font-weight:bold;">PA_SU_HARDWARE_SCREEN_OFFSET</span> &lt;- HW_SCREEN_OFFSET_X = 0
                                        HW_SCREEN_OFFSET_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_NANINF_CNTL</span> &lt;- VTE_XY_INF_DISCARD = 0
                             VTE_Z_INF_DISCARD = 0
                             VTE_W_INF_DISCARD = 0
                             VTE_0XNANINF_IS_0 = 0
                             VTE_XY_NAN_RETAIN = 0
                             VTE_Z_NAN_RETAIN = 0
                             VTE_W_NAN_RETAIN = 0
                             VTE_W_RECIP_NAN_IS_0 = 0
                             VS_XY_NAN_TO_INF = 0
                             VS_XY_INF_RETAIN = 0
                             VS_Z_NAN_TO_INF = 0
                             VS_Z_INF_RETAIN = 0
                             VS_W_NAN_TO_INF = 0
                             VS_W_INF_RETAIN = 0
                             VS_CLIP_DIST_INF_DISCARD = 0
                             VTE_NO_OUTPUT_NEG_0 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE0</span> &lt;- COMPAREFUNC0 = REF_NEVER
                                      COMPAREVALUE0 = 0
                                      COMPAREMASK0 = 0
                                      ENABLE0 = 0
        <span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE1</span> &lt;- COMPAREFUNC1 = REF_NEVER
                                      COMPAREVALUE1 = 0
                                      COMPAREMASK1 = 0
                                      ENABLE1 = 0
        <span style="color:yellow;font-weight:bold;">DB_PRELOAD_CONTROL</span> &lt;- START_X = 0
                              START_Y = 0
                              MAX_X = 0
                              MAX_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE</span> &lt;- FORCE_HIZ_ENABLE = FORCE_OFF
                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
                              FORCE_SHADER_Z_ORDER = 0
                              FAST_Z_DISABLE = 0
                              FAST_STENCIL_DISABLE = 0
                              NOOP_CULL_DISABLE = 0
                              FORCE_COLOR_KILL = 0
                              FORCE_Z_READ = 0
                              FORCE_STENCIL_READ = 0
                              FORCE_FULL_Z_RANGE = FORCE_OFF
                              FORCE_QC_SMASK_CONFLICT = 0
                              DISABLE_VIEWPORT_CLAMP = 0
                              IGNORE_SC_ZRANGE = 0
                              DISABLE_FULLY_COVERED = 0
                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
                              MAX_TILES_IN_DTT = 0
                              DISABLE_TILE_RATE_TILES = 0
                              FORCE_Z_DIRTY = 0
                              FORCE_STENCIL_DIRTY = 0
                              FORCE_Z_VALID = 0
                              FORCE_STENCIL_VALID = 0
                              PRESERVE_COMPRESSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MAX_VTX_INDX</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">VGT_MIN_VTX_INDX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">VGT_INDX_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">TA_BC_BASE_ADDR</span> &lt;- 0x00008100
------------------- IB2: Init config end -------------------

------------------ IB begin ------------------
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00820000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000001
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 1
        This trace point was reached by the CP.</span>
<span style="color:lime;font-weight:bold;">CONTEXT_CONTROL</span>:
        0x80000000
        0x80000000
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_HOS_MAX_TESS_LEVEL</span> &lt;- 64.0f (0x42800000)
        <span style="color:yellow;font-weight:bold;">VGT_HOS_MIN_TESS_LEVEL</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_PER_ES</span> &lt;- GS_PER_ES = 128 (0x80)
        <span style="color:yellow;font-weight:bold;">VGT_ES_PER_GS</span> &lt;- ES_PER_GS = 64 (0x40)
        <span style="color:yellow;font-weight:bold;">VGT_GS_PER_VS</span> &lt;- GS_PER_VS = 2
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_RESET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_DRAW_OPAQUE_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_VTX_CNT_EN</span> &lt;- VTX_CNT_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_ENHANCE</span> &lt;- CLIP_VTX_REORDER_ENA = 1
                         NUM_CLIP_SEQ = 3
                         CLIPPED_PRIM_SEQ_STALL = 0
                         VE_NAN_PROC_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_0</span> &lt;- DISTANCE_0 = 0
                                     DISTANCE_1 = 1
                                     DISTANCE_2 = 2
                                     DISTANCE_3 = 3
                                     DISTANCE_4 = 4
                                     DISTANCE_5 = 5
                                     DISTANCE_6 = 6
                                     DISTANCE_7 = 7
        <span style="color:yellow;font-weight:bold;">PA_SC_CENTROID_PRIORITY_1</span> &lt;- DISTANCE_8 = 8
                                     DISTANCE_9 = 9
                                     DISTANCE_10 = 10 (0xa)
                                     DISTANCE_11 = 11 (0xb)
                                     DISTANCE_12 = 12 (0xc)
                                     DISTANCE_13 = 13 (0xd)
                                     DISTANCE_14 = 14 (0xe)
                                     DISTANCE_15 = 15 (0xf)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_PRIM_FILTER_CNTL</span> &lt;- TRIANGLE_FILTER_DISABLE = 0
                                  LINE_FILTER_DISABLE = 0
                                  POINT_FILTER_DISABLE = 0
                                  RECTANGLE_FILTER_DISABLE = 0
                                  TRIANGLE_EXPAND_ENA = 0
                                  LINE_EXPAND_ENA = 0
                                  POINT_EXPAND_ENA = 0
                                  RECTANGLE_EXPAND_ENA = 0
                                  PRIM_EXPAND_CONSTANT = 0
                                  XMAX_RIGHT_EXCLUSION = 0
                                  YMAX_BOTTOM_EXCLUSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_0</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_0</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_1</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_1</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_2</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_3</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_3</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_4</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_4</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_5</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_5</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_6</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_6</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_7</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_7</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_8</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_8</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_9</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_9</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_10</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_10</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_11</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_11</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_12</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_12</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_13</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_13</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_14</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_14</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMIN_15</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_ZMAX_15</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_SC_RASTER_CONFIG</span> &lt;- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_2
                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_2
                               RB_XSEL = 1
                               RB_YSEL = 0
                               PKR_MAP = RASTER_CONFIG_PKR_MAP_2
                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_1
                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
                               SC_MAP = RASTER_CONFIG_SC_MAP_0
                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
                               SE_MAP = RASTER_CONFIG_SE_MAP_2
                               SE_XSEL = RASTER_CONFIG_SE_XSEL_32_WIDE_TILE
                               SE_YSEL = RASTER_CONFIG_SE_YSEL_32_WIDE_TILE
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
                                   WINDOW_OFFSET_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_GENERIC_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                    BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_TL</span> &lt;- TL_X = 0
                                   TL_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_SCREEN_SCISSOR_BR</span> &lt;- BR_X = 16384 (0x4000)
                                   BR_Y = 16384 (0x4000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_CLIPRECT_RULE</span> &lt;- CLIP_RULE = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_EDGERULE</span> &lt;- ER_TRI = 10 (0xa)
                          ER_POINT = 10 (0xa)
                          ER_RECT = 10 (0xa)
                          ER_LINE_LR = 42 (0x2a)
                          ER_LINE_RL = 42 (0x2a)
                          ER_LINE_TB = 10 (0xa)
                          ER_LINE_BT = 10 (0xa)
        <span style="color:yellow;font-weight:bold;">PA_SU_HARDWARE_SCREEN_OFFSET</span> &lt;- HW_SCREEN_OFFSET_X = 0
                                        HW_SCREEN_OFFSET_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_NANINF_CNTL</span> &lt;- VTE_XY_INF_DISCARD = 0
                             VTE_Z_INF_DISCARD = 0
                             VTE_W_INF_DISCARD = 0
                             VTE_0XNANINF_IS_0 = 0
                             VTE_XY_NAN_RETAIN = 0
                             VTE_Z_NAN_RETAIN = 0
                             VTE_W_NAN_RETAIN = 0
                             VTE_W_RECIP_NAN_IS_0 = 0
                             VS_XY_NAN_TO_INF = 0
                             VS_XY_INF_RETAIN = 0
                             VS_Z_NAN_TO_INF = 0
                             VS_Z_INF_RETAIN = 0
                             VS_W_NAN_TO_INF = 0
                             VS_W_INF_RETAIN = 0
                             VS_CLIP_DIST_INF_DISCARD = 0
                             VTE_NO_OUTPUT_NEG_0 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE0</span> &lt;- COMPAREFUNC0 = REF_NEVER
                                      COMPAREVALUE0 = 0
                                      COMPAREMASK0 = 0
                                      ENABLE0 = 0
        <span style="color:yellow;font-weight:bold;">DB_SRESULTS_COMPARE_STATE1</span> &lt;- COMPAREFUNC1 = REF_NEVER
                                      COMPAREVALUE1 = 0
                                      COMPAREMASK1 = 0
                                      ENABLE1 = 0
        <span style="color:yellow;font-weight:bold;">DB_PRELOAD_CONTROL</span> &lt;- START_X = 0
                              START_Y = 0
                              MAX_X = 0
                              MAX_Y = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE</span> &lt;- FORCE_HIZ_ENABLE = FORCE_OFF
                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
                              FORCE_SHADER_Z_ORDER = 0
                              FAST_Z_DISABLE = 0
                              FAST_STENCIL_DISABLE = 0
                              NOOP_CULL_DISABLE = 0
                              FORCE_COLOR_KILL = 0
                              FORCE_Z_READ = 0
                              FORCE_STENCIL_READ = 0
                              FORCE_FULL_Z_RANGE = FORCE_OFF
                              FORCE_QC_SMASK_CONFLICT = 0
                              DISABLE_VIEWPORT_CLAMP = 0
                              IGNORE_SC_ZRANGE = 0
                              DISABLE_FULLY_COVERED = 0
                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
                              MAX_TILES_IN_DTT = 0
                              DISABLE_TILE_RATE_TILES = 0
                              FORCE_Z_DIRTY = 0
                              FORCE_STENCIL_DIRTY = 0
                              FORCE_Z_VALID = 0
                              FORCE_STENCIL_VALID = 0
                              PRESERVE_COMPRESSION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MAX_VTX_INDX</span> &lt;- 0xffffffff
        <span style="color:yellow;font-weight:bold;">VGT_MIN_VTX_INDX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">VGT_INDX_OFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">TA_BC_BASE_ADDR</span> &lt;- 0x00008100
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = SAMPLE_STREAMOUTSTATS
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 3
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">ADDRESS_LO</span> &lt;- 0x00824020
        <span style="color:yellow;font-weight:bold;">ADDRESS_HI</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = PIPELINESTAT_START
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_BUFFER_CONFIG</span> &lt;- STREAM_0_BUFFER_EN = 0
                                     STREAM_1_BUFFER_EN = 0
                                     STREAM_2_BUFFER_EN = 0
                                     STREAM_3_BUFFER_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_STRMOUT_CONFIG</span> &lt;- STREAMOUT_0_EN = 1
                              STREAMOUT_1_EN = 1
                              STREAMOUT_2_EN = 1
                              STREAMOUT_3_EN = 1
                              RAST_STREAM = 0
                              RAST_STREAM_MASK = 0
                              USE_RAST_STREAM_MASK = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR0_BASE</span> &lt;- 0x00008280
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_PITCH</span> &lt;- TILE_MAX = 31 (0x1f)
                           FMASK_TILE_MAX = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_SLICE</span> &lt;- TILE_MAX = 1023 (0x003ff)
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_VIEW</span> &lt;- SLICE_START = 0
                          SLICE_MAX = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_ATTRIB</span> &lt;- TILE_MODE_INDEX = 16 (0x10)
                            FMASK_TILE_MODE_INDEX = 16 (0x10)
                            FMASK_BANK_HEIGHT = 0
                            NUM_SAMPLES = 0
                            NUM_FRAGMENTS = 0
                            FORCE_DST_ALPHA_1 = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_DCC_CONTROL</span> &lt;- OVERWRITE_COMBINER_DISABLE = 0
                                 KEY_CLEAR_ENABLE = 0
                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
                                 MIN_COMPRESSED_BLOCK_SIZE = 0
                                 MAX_COMPRESSED_BLOCK_SIZE = 0
                                 COLOR_TRANSFORM = 0
                                 INDEPENDENT_64B_BLOCKS = 0
                                 LOSSY_RGB_PRECISION = 0
                                 LOSSY_ALPHA_PRECISION = 0
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CMASK</span> &lt;- 0x00008230
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CMASK_SLICE</span> &lt;- TILE_MAX = 7
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_FMASK</span> &lt;- 0x00008280
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_FMASK_SLICE</span> &lt;- TILE_MAX = 1023 (0x003ff)
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CLEAR_WORD0</span> &lt;- 0x1a1a1a1a
        <span style="color:yellow;font-weight:bold;">CB_COLOR0_CLEAR_WORD1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR1_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_8_8_8_8
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 1
                          COMPRESSION = 0
                          BLEND_CLAMP = 1
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR2_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR3_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR4_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR5_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR6_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR7_INFO</span> &lt;- ENDIAN = ENDIAN_NONE
                          FORMAT = COLOR_INVALID
                          LINEAR_GENERAL = 0
                          NUMBER_TYPE = NUMBER_UNORM
                          COMP_SWAP = SWAP_STD
                          FAST_CLEAR = 0
                          COMPRESSION = 0
                          BLEND_CLAMP = 0
                          BLEND_BYPASS = 0
                          SIMPLE_FLOAT = 0
                          ROUND_MODE = 0
                          CMASK_IS_LINEAR = 0
                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
                          FMASK_COMPRESSION_DISABLE = 0
                          FMASK_COMPRESS_1FRAG_ONLY = 0
                          DCC_ENABLE = 0
                          CMASK_ADDR_TYPE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_Z_INFO</span> &lt;- FORMAT = Z_INVALID
                     NUM_SAMPLES = 0
                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                     TILE_MODE_INDEX = 0
                     DECOMPRESS_ON_N_ZPLANES = 0
                     ALLOW_EXPCLEAR = 0
                     READ_SIZE = 0
                     TILE_SURFACE_ENABLE = 0
                     CLEAR_DISALLOWED = 0
                     ZRANGE_PRECISION = 0
        <span style="color:yellow;font-weight:bold;">DB_STENCIL_INFO</span> &lt;- FORMAT = STENCIL_INVALID
                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
                           TILE_MODE_INDEX = 0
                           ALLOW_EXPCLEAR = 0
                           TILE_STENCIL_DISABLE = 0
                           CLEAR_DISALLOWED = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_WINDOW_SCISSOR_BR</span> &lt;- BR_X = 256 (0x100)
                                   BR_Y = 256 (0x100)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0</span> &lt;- S0_X = 1
                                             S0_Y = 13 (0xd)
                                             S1_X = 15 (0xf)
                                             S1_Y = 3
                                             S2_X = 5
                                             S2_Y = 1
                                             S3_X = 13 (0xd)
                                             S3_Y = 11 (0xb)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1</span> &lt;- S4_X = 11 (0xb)
                                             S4_Y = 5
                                             S5_X = 9
                                             S5_Y = 15 (0xf)
                                             S6_X = 3
                                             S6_Y = 7
                                             S7_X = 7
                                             S7_Y = 9
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0</span> &lt;- S0_X = 1
                                             S0_Y = 13 (0xd)
                                             S1_X = 15 (0xf)
                                             S1_Y = 3
                                             S2_X = 5
                                             S2_Y = 1
                                             S3_X = 13 (0xd)
                                             S3_Y = 11 (0xb)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1</span> &lt;- S4_X = 11 (0xb)
                                             S4_Y = 5
                                             S5_X = 9
                                             S5_Y = 15 (0xf)
                                             S6_X = 3
                                             S6_Y = 7
                                             S7_X = 7
                                             S7_Y = 9
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0</span> &lt;- S0_X = 1
                                             S0_Y = 13 (0xd)
                                             S1_X = 15 (0xf)
                                             S1_Y = 3
                                             S2_X = 5
                                             S2_Y = 1
                                             S3_X = 13 (0xd)
                                             S3_Y = 11 (0xb)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1</span> &lt;- S4_X = 11 (0xb)
                                             S4_Y = 5
                                             S5_X = 9
                                             S5_Y = 15 (0xf)
                                             S6_X = 3
                                             S6_Y = 7
                                             S7_X = 7
                                             S7_Y = 9
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2</span> &lt;- S8_X = 0
                                             S8_Y = 0
                                             S9_X = 0
                                             S9_Y = 0
                                             S10_X = 0
                                             S10_Y = 0
                                             S11_X = 0
                                             S11_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3</span> &lt;- S12_X = 0
                                             S12_Y = 0
                                             S13_X = 0
                                             S13_Y = 0
                                             S14_X = 0
                                             S14_Y = 0
                                             S15_X = 0
                                             S15_Y = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0</span> &lt;- S0_X = 1
                                             S0_Y = 13 (0xd)
                                             S1_X = 15 (0xf)
                                             S1_Y = 3
                                             S2_X = 5
                                             S2_Y = 1
                                             S3_X = 13 (0xd)
                                             S3_Y = 11 (0xb)
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1</span> &lt;- S4_X = 11 (0xb)
                                             S4_Y = 5
                                             S5_X = 9
                                             S5_Y = 15 (0xf)
                                             S6_X = 3
                                             S6_Y = 7
                                             S7_X = 7
                                             S7_Y = 9
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_CONTROL</span> &lt;- DEPTH_CLEAR_ENABLE = 0
                             STENCIL_CLEAR_ENABLE = 0
                             DEPTH_COPY = 0
                             STENCIL_COPY = 0
                             RESUMMARIZE_ENABLE = 0
                             STENCIL_COMPRESS_DISABLE = 0
                             DEPTH_COMPRESS_DISABLE = 0
                             COPY_CENTROID = 0
                             COPY_SAMPLE = 0
                             DECOMPRESS_ENABLE = 0
        <span style="color:yellow;font-weight:bold;">DB_COUNT_CONTROL</span> &lt;- ZPASS_INCREMENT_DISABLE = 1
                            PERFECT_ZPASS_COUNTS = 0
                            SAMPLE_RATE = 0
                            ZPASS_ENABLE = 0
                            ZFAIL_ENABLE = 0
                            SFAIL_ENABLE = 0
                            DBFAIL_ENABLE = 0
                            SLICE_EVEN_ENABLE = 0
                            SLICE_ODD_ENABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_RENDER_OVERRIDE2</span> &lt;- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
                               DISABLE_COLOR_ON_VALIDATION = 0
                               DECOMPRESS_Z_ON_FLUSH = 0
                               DISABLE_REG_SNOOP = 0
                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
                               SEPARATE_HIZS_FUNC_ENABLE = 0
                               HIZ_ZFUNC = 0
                               HIS_SFUNC_FF = 0
                               HIS_SFUNC_BF = 0
                               PRESERVE_ZRANGE = 0
                               PRESERVE_SRESULTS = 0
                               DISABLE_FAST_PASS = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_SHADER_CONTROL</span> &lt;- Z_EXPORT_ENABLE = 0
                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
                             Z_ORDER = LATE_Z
                             KILL_ENABLE = 0
                             COVERAGE_TO_MASK_ENABLE = 0
                             MASK_EXPORT_ENABLE = 0
                             EXEC_ON_HIER_FAIL = 0
                             EXEC_ON_NOOP = 0
                             ALPHA_TO_MASK_DISABLE = 0
                             DEPTH_BEFORE_SHADER = 0
                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
                             DUAL_QUAD_DISABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_LINE_CNTL</span> &lt;- EXPAND_LINE_WIDTH = 0
                           LAST_PIXEL = 1
                           PERPENDICULAR_ENDCAP_ENA = 0
                           DX10_DIAMOND_TEST_ENA = 0
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_CONFIG</span> &lt;- MSAA_NUM_SAMPLES = 0
                           AA_MASK_CENTROID_DTMN = 0
                           MAX_SAMPLE_DIST = 0
                           MSAA_EXPOSED_SAMPLES = 0
                           DETAIL_TO_EXPOSED_MODE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_EQAA</span> &lt;- MAX_ANCHOR_SAMPLES = 0
                   PS_ITER_SAMPLES = 0
                   MASK_EXPORT_NUM_SAMPLES = 0
                   ALPHA_TO_MASK_NUM_SAMPLES = 0
                   HIGH_QUALITY_INTERSECTIONS = 1
                   INCOHERENT_EQAA_READS = 0
                   INTERPOLATE_COMP_Z = 0
                   INTERPOLATE_SRC_Z = 0
                   STATIC_ANCHOR_ASSOCIATIONS = 1
                   ALPHA_TO_MASK_EQAA_DISABLE = 0
                   OVERRASTERIZATION_AMOUNT = 0
                   ENABLE_POSTZ_OVERRASTERIZATION = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_MODE_CNTL_1</span> &lt;- WALK_SIZE = 0
                             WALK_ALIGNMENT = 0
                             WALK_ALIGN8_PRIM_FITS_ST = 0
                             WALK_FENCE_ENABLE = 0
                             WALK_FENCE_SIZE = 0
                             SUPERTILE_WALK_ORDER_ENABLE = 0
                             TILE_WALK_ORDER_ENABLE = 0
                             TILE_COVER_DISABLE = 0
                             TILE_COVER_NO_SCISSOR = 0
                             ZMM_LINE_EXTENT = 0
                             ZMM_LINE_OFFSET = 0
                             ZMM_RECT_EXTENT = 0
                             KILL_PIX_POST_HI_Z = 0
                             KILL_PIX_POST_DETAIL_MASK = 0
                             PS_ITER_SAMPLE = 0
                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
                             MULTI_GPU_SUPERTILE_ENABLE = 0
                             GPU_ID_OVERRIDE_ENABLE = 0
                             GPU_ID_OVERRIDE = 0
                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
                             FORCE_EOV_CNTDWN_ENABLE = 1
                             FORCE_EOV_REZ_ENABLE = 1
                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
                             OUT_OF_ORDER_WATER_MARK = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_AA_MASK_X0Y0_X1Y0</span> &lt;- AA_MASK_X0Y0 = 0xffff
                                   AA_MASK_X1Y0 = 0xffff
        <span style="color:yellow;font-weight:bold;">PA_SC_AA_MASK_X0Y1_X1Y1</span> &lt;- AA_MASK_X0Y1 = 0xffff
                                   AA_MASK_X1Y1 = 0xffff
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_TARGET_MASK</span> &lt;- TARGET0_ENABLE = 15 (0xf)
                          TARGET1_ENABLE = 0
                          TARGET2_ENABLE = 0
                          TARGET3_ENABLE = 0
                          TARGET4_ENABLE = 0
                          TARGET5_ENABLE = 0
                          TARGET6_ENABLE = 0
                          TARGET7_ENABLE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_BLEND_RED</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_GREEN</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_BLUE</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND_ALPHA</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VS_OUT_CNTL</span> &lt;- CLIP_DIST_ENA_0 = 0
                             CLIP_DIST_ENA_1 = 0
                             CLIP_DIST_ENA_2 = 0
                             CLIP_DIST_ENA_3 = 0
                             CLIP_DIST_ENA_4 = 0
                             CLIP_DIST_ENA_5 = 0
                             CLIP_DIST_ENA_6 = 0
                             CLIP_DIST_ENA_7 = 0
                             CULL_DIST_ENA_0 = 0
                             CULL_DIST_ENA_1 = 0
                             CULL_DIST_ENA_2 = 0
                             CULL_DIST_ENA_3 = 0
                             CULL_DIST_ENA_4 = 0
                             CULL_DIST_ENA_5 = 0
                             CULL_DIST_ENA_6 = 0
                             CULL_DIST_ENA_7 = 0
                             USE_VTX_POINT_SIZE = 0
                             USE_VTX_EDGE_FLAG = 0
                             USE_VTX_RENDER_TARGET_INDX = 0
                             USE_VTX_VIEWPORT_INDX = 0
                             USE_VTX_KILL_FLAG = 0
                             VS_OUT_MISC_VEC_ENA = 0
                             VS_OUT_CCDIST0_VEC_ENA = 0
                             VS_OUT_CCDIST1_VEC_ENA = 0
                             VS_OUT_MISC_SIDE_BUS_ENA = 1
                             USE_VTX_GS_CUT_FLAG = 0
                             USE_VTX_LINE_WIDTH = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_CLIP_CNTL</span> &lt;- UCP_ENA_0 = 0
                           UCP_ENA_1 = 0
                           UCP_ENA_2 = 0
                           UCP_ENA_3 = 0
                           UCP_ENA_4 = 0
                           UCP_ENA_5 = 0
                           PS_UCP_Y_SCALE_NEG = 0
                           PS_UCP_MODE = 3
                           CLIP_DISABLE = 0
                           UCP_CULL_ONLY_ENA = 0
                           BOUNDARY_EDGE_FLAG_ENA = 0
                           DX_CLIP_SPACE_DEF = 0
                           DIS_CLIP_ERR_DETECT = 0
                           VTX_KILL_OR = 0
                           DX_RASTERIZATION_KILL = 1
                           DX_LINEAR_ATTR_CLIP_ENA = 1
                           VTE_VPORT_PROVOKE_DISABLE = 0
                           ZCLIP_NEAR_DISABLE = 1
                           ZCLIP_FAR_DISABLE = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_REUSE_OFF</span> &lt;- REUSE_OFF = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_0_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_1_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_2_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_3_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_4_W</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_X</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_Y</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_Z</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">PA_CL_UCP_5_W</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_0</span> &lt;- 0x0086c900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_0</span> &lt;- 0x0086c900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_0</span> &lt;- 0x0086c900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_ES_0</span> &lt;- 0x0086c900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_ES_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_0</span> &lt;- 0x0086c900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_1</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_2</span> &lt;- 0x00868100
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_8</span> &lt;- 0x00868200
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_9</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_4</span> &lt;- 0x00868300
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_6</span> &lt;- 0x00868b00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_2</span> &lt;- 0x00868d00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_8</span> &lt;- 0x00868e00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_9</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_4</span> &lt;- 0x00868f00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_6</span> &lt;- 0x00869700
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_PS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_2</span> &lt;- 0x00869900
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_8</span> &lt;- 0x00869a00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_9</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_4</span> &lt;- 0x00869b00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_6</span> &lt;- 0x0086a300
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_GS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_2</span> &lt;- 0x0086a500
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_3</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_8</span> &lt;- 0x0086a600
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_9</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_4</span> &lt;- 0x0086a700
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_5</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_6</span> &lt;- 0x0086af00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_HS_7</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_10</span> &lt;- 0x0086cb00
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_11</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_VPORT_SCISSOR_0_TL</span> &lt;- TL_X = 0
                                    TL_Y = 0
                                    WINDOW_OFFSET_DISABLE = 1
        <span style="color:yellow;font-weight:bold;">PA_SC_VPORT_SCISSOR_0_BR</span> &lt;- BR_X = 256 (0x100)
                                    BR_Y = 256 (0x100)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_CLIP_ADJ</span> &lt;- 0x437efe00
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_VERT_DISC_ADJ</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_CLIP_ADJ</span> &lt;- 0x437efe00
        <span style="color:yellow;font-weight:bold;">PA_CL_GB_HORZ_DISC_ADJ</span> &lt;- 1.0f (0x3f800000)
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VPORT_XSCALE</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_XOFFSET</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_YSCALE</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_YOFFSET</span> &lt;- 128.0f (0x43000000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_ZSCALE</span> &lt;- 1.0f (0x3f800000)
        <span style="color:yellow;font-weight:bold;">PA_CL_VPORT_ZOFFSET</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_STENCILREFMASK</span> &lt;- STENCILTESTVAL = 0
                             STENCILMASK = 0
                             STENCILWRITEMASK = 0
                             STENCILOPVAL = 1
        <span style="color:yellow;font-weight:bold;">DB_STENCILREFMASK_BF</span> &lt;- STENCILTESTVAL_BF = 0
                                STENCILMASK_BF = 0
                                STENCILWRITEMASK_BF = 0
                                STENCILOPVAL_BF = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_ALPHA_TO_MASK</span> &lt;- ALPHA_TO_MASK_ENABLE = 0
                            ALPHA_TO_MASK_OFFSET0 = 2
                            ALPHA_TO_MASK_OFFSET1 = 2
                            ALPHA_TO_MASK_OFFSET2 = 2
                            ALPHA_TO_MASK_OFFSET3 = 2
                            OFFSET_ROUND = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_BLEND0_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND1_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND2_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND3_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND4_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND5_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND6_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
        <span style="color:yellow;font-weight:bold;">CB_BLEND7_CONTROL</span> &lt;- COLOR_SRCBLEND = BLEND_ZERO
                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
                             COLOR_DESTBLEND = BLEND_ZERO
                             ALPHA_SRCBLEND = BLEND_ZERO
                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
                             ALPHA_DESTBLEND = BLEND_ZERO
                             SEPARATE_ALPHA_BLEND = 0
                             ENABLE = 0
                             DISABLE_ROP3 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">CB_COLOR_CONTROL</span> &lt;- DISABLE_DUAL_QUAD = 0
                            DEGAMMA_ENABLE = 0
                            MODE = CB_NORMAL
                            ROP3 = X_0XCC
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_INTERP_CONTROL_0</span> &lt;- FLAT_SHADE_ENA = 1
                                PNT_SPRITE_ENA = 1
                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
                                PNT_SPRITE_TOP_1 = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_POINT_SIZE</span> &lt;- HEIGHT = 0
                            WIDTH = 0
        <span style="color:yellow;font-weight:bold;">PA_SU_POINT_MINMAX</span> &lt;- MIN_SIZE = 0
                              MAX_SIZE = 0
        <span style="color:yellow;font-weight:bold;">PA_SU_LINE_CNTL</span> &lt;- WIDTH = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SC_MODE_CNTL_0</span> &lt;- MSAA_ENABLE = 0
                             VPORT_SCISSOR_ENABLE = 1
                             LINE_STIPPLE_ENABLE = 0
                             SEND_UNLIT_STILES_TO_PKR = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_VTX_CNTL</span> &lt;- PIX_CENTER = 0
                          ROUND_MODE = X_TRUNCATE
                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_POLY_OFFSET_CLAMP</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_SU_SC_MODE_CNTL</span> &lt;- CULL_FRONT = 0
                              CULL_BACK = 0
                              FACE = 1
                              POLY_MODE = X_DISABLE_POLY_MODE
                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
                              POLY_OFFSET_FRONT_ENABLE = 0
                              POLY_OFFSET_BACK_ENABLE = 0
                              POLY_OFFSET_PARA_ENABLE = 0
                              VTX_WINDOW_OFFSET_ENABLE = 0
                              PROVOKING_VTX_LAST = 1
                              PERSP_CORR_DIS = 0
                              MULTI_PRIM_IB_ENA = 0
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_14</span> &lt;- 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_DEPTH_CONTROL</span> &lt;- STENCIL_ENABLE = 0
                            Z_ENABLE = 0
                            Z_WRITE_ENABLE = 0
                            DEPTH_BOUNDS_ENABLE = 0
                            ZFUNC = FRAG_NEVER
                            BACKFACE_ENABLE = 0
                            STENCILFUNC = REF_NEVER
                            STENCILFUNC_BF = REF_NEVER
                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">DB_STENCIL_CONTROL</span> &lt;- STENCILFAIL = STENCIL_KEEP
                              STENCILZPASS = STENCIL_KEEP
                              STENCILZFAIL = STENCIL_KEEP
                              STENCILFAIL_BF = STENCIL_KEEP
                              STENCILZPASS_BF = STENCIL_KEEP
                              STENCILZFAIL_BF = STENCIL_KEEP
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_SHADER_STAGES_EN</span> &lt;- LS_EN = LS_STAGE_OFF
                                HS_EN = 0
                                ES_EN = ES_STAGE_OFF
                                GS_EN = 0
                                VS_EN = VS_STAGE_REAL
                                DYNAMIC_HS = 0
                                DISPATCH_DRAW_EN = 0
                                DIS_DEALLOC_ACCUM_0 = 0
                                DIS_DEALLOC_ACCUM_1 = 0
                                VS_WAVE_ID_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_MODE</span> &lt;- MODE = GS_OFF
                       RESERVED_0 = 0
                       CUT_MODE = GS_CUT_1024
                       RESERVED_1 = 0
                       GS_C_PACK_EN = 0
                       RESERVED_2 = 0
                       ES_PASSTHRU = 0
                       COMPUTE_MODE = 0
                       FAST_COMPUTE_MODE = 0
                       ELEMENT_INFO_EN = 0
                       PARTIAL_THD_AT_EOI = 0
                       SUPPRESS_CUTS = 0
                       ES_WRITE_OPTIMIZE = 0
                       GS_WRITE_OPTIMIZE = 0
                       ONCHIP = X_0_OFFCHIP_GS
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVEID_EN</span> &lt;- PRIMITIVEID_EN = 0
                              DISABLE_RESET_ON_EOI = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_VS_OUT_CONFIG</span> &lt;- VS_EXPORT_COUNT = 0
                             VS_HALF_PACK = 0
                             VS_EXPORTS_FOG = 0
                             VS_OUT_FOG_VEC_ADDR = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_POS_FORMAT</span> &lt;- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_LO_VS</span> &lt;- 0x00008250
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_HI_VS</span> &lt;- MEM_BASE = 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_RSRC1_VS</span> &lt;- VGPRS = 3
                                   SGPRS = 2
                                   PRIORITY = 0
                                   FLOAT_MODE = 192 (0xc0)
                                   PRIV = 0
                                   DX10_CLAMP = 1
                                   DEBUG_MODE = 0
                                   IEEE_MODE = 0
                                   VGPR_COMP_CNT = 0
                                   CU_GROUP_ENABLE = 0
                                   CACHE_CTL = 0
                                   CDBG_USER = 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_PGM_RSRC2_VS</span> &lt;- SCRATCH_EN = 0
                                   USER_SGPR = 15 (0xf)
                                   TRAP_PRESENT = 0
                                   OC_LDS_EN = 0
                                   SO_BASE0_EN = 0
                                   SO_BASE1_EN = 0
                                   SO_BASE2_EN = 0
                                   SO_BASE3_EN = 0
                                   SO_EN = 0
                                   EXCP_EN = 0
                                   EXCP_EN_CIK = 0
                                   DISPATCH_DRAW_EN = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">PA_CL_VTE_CNTL</span> &lt;- VPORT_X_SCALE_ENA = 1
                          VPORT_X_OFFSET_ENA = 1
                          VPORT_Y_SCALE_ENA = 1
                          VPORT_Y_OFFSET_ENA = 1
                          VPORT_Z_SCALE_ENA = 1
                          VPORT_Z_OFFSET_ENA = 1
                          VTX_XY_FMT = 0
                          VTX_Z_FMT = 0
                          VTX_W0_FMT = 1
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_TMPRING_SIZE</span> &lt;- WAVES = 768 (0x300)
                            WAVESIZE = 0
<span style="color:aqua;font-weight:bold;">SET_CONFIG_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_PRIMITIVE_TYPE</span> &lt;- PRIM_TYPE = DI_PT_QUADLIST
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">IA_MULTI_VGT_PARAM</span> &lt;- PRIMGROUP_SIZE = 127 (0x007f)
                              PARTIAL_VS_WAVE_ON = 0
                              SWITCH_ON_EOP = 0
                              PARTIAL_ES_WAVE_ON = 0
                              SWITCH_ON_EOI = 0
                              WD_SWITCH_ON_EOP = 0
                              MAX_PRIMGRP_IN_WAVE = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_LS_HS_CONFIG</span> &lt;- NUM_PATCHES = 0
                            HS_NUM_INPUT_CP = 0
                            HS_NUM_OUTPUT_CP = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_GS_OUT_PRIM_TYPE</span> &lt;- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
                                OUTPRIM_TYPE_1 = 0
                                OUTPRIM_TYPE_2 = 0
                                OUTPRIM_TYPE_3 = 0
                                UNIQUE_TYPE_PER_STREAM = 0
<span style="color:aqua;font-weight:bold;">SET_CONTEXT_REG:
        </span><span style="color:yellow;font-weight:bold;">VGT_MULTI_PRIM_IB_RESET_EN</span> &lt;- RESET_EN = 0
<span style="color:lime;font-weight:bold;">NUM_INSTANCES</span>:
        <span style="color:yellow;font-weight:bold;">VGT_NUM_INSTANCES</span> &lt;- 1
<span style="color:aqua;font-weight:bold;">SET_SH_REG:
        </span><span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_12</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">SPI_SHADER_USER_DATA_VS_13</span> &lt;- 0
<span style="color:lime;font-weight:bold;">DRAW_INDEX_AUTO</span>:
        <span style="color:yellow;font-weight:bold;">VGT_NUM_INDICES</span> &lt;- 4
        <span style="color:yellow;font-weight:bold;">VGT_DRAW_INITIATOR</span> &lt;- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
                              MAJOR_MODE = DI_MAJOR_MODE_0
                              NOT_EOP = 0
                              USE_OPAQUE = 0
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00820000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000002
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 2
        !!!!! This is the last trace point that was reached by the CP !!!!!</span>
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = SAMPLE_STREAMOUTSTATS
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 3
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
        <span style="color:yellow;font-weight:bold;">ADDRESS_LO</span> &lt;- 0x00824030
        <span style="color:yellow;font-weight:bold;">ADDRESS_HI</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = PS_PARTIAL_FLUSH
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 4
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">EVENT_WRITE</span>:
        <span style="color:yellow;font-weight:bold;">VGT_EVENT_INITIATOR</span> &lt;- EVENT_TYPE = CS_PARTIAL_FLUSH
        <span style="color:yellow;font-weight:bold;">EVENT_INDEX</span> &lt;- 4
        <span style="color:yellow;font-weight:bold;">INV_L2</span> &lt;- 0
<span style="color:lime;font-weight:bold;">PFP_SYNC_ME</span>:
        0x00000000
<span style="color:lime;font-weight:bold;">WRITE_DATA</span>:
        <span style="color:yellow;font-weight:bold;">CONTROL</span> &lt;- ENGINE_SEL = ME
                   WR_CONFIRM = 1
                   WR_ONE_ADDR = 0
                   DST_SEL = MEMORY_SYNC
        <span style="color:yellow;font-weight:bold;">DST_ADDR_LO</span> &lt;- 0x00820000
        <span style="color:yellow;font-weight:bold;">DST_ADDR_HI</span> &lt;- 0
        0x00000003
<span style="color:lime;font-weight:bold;">NOP</span>:
        <span style="color:red;">Trace point ID: 3
        !!!!! This trace point was NOT reached by the CP !!!!!</span>
------------------- IB end -------------------

Done.
</pre>
</body>
</html>

Attachment #124324
dmesg after the mesa dump	text/plain	2016-06-05 02:23:17 UTC	62.29 KB	no flags	Details

Attachment #127226
Xorg log with lastest 4.9-wip kernel and mesa master branch	text/plain	2016-10-11 20:30:58 UTC	21.03 KB	no flags	Details

Attachment #128182
openSuse Tumbleweed - Linux 4.8.10	text/x-log	2016-11-25 07:19:47 UTC	225.99 KB	no flags	Details

Attachment #128452
dmesg for linux 4.9 amdgpu driver	text/plain	2016-12-13 18:27:20 UTC	62.60 KB	no flags	Details

Attachment #133231
dmesg amdgpu kernel 4.10	text/plain	2017-08-03 21:10:37 UTC	73.72 KB	no flags	Details

Attachment #133232
Xorg.log amdgpu kernel 4.10	text/plain	2017-08-03 21:11:56 UTC	24.86 KB	no flags	Details

Attachment #133233
dmesg radeon kernel 4.10	text/plain	2017-08-03 21:14:45 UTC	88.80 KB	no flags	Details

Attachment #134388
dmesg radeon kernel 4.12.13	text/plain	2017-09-20 19:47:34 UTC	69.35 KB	no flags	Details

Attachment #134576
journalctl -k amdgpu with linux-amd-staging-git	text/plain	2017-09-30 14:58:24 UTC	74.93 KB	no flags	Details

Attachment #135238
journalctl_radeon_4.14.0-041400rc7	text/x-log	2017-11-04 20:45:17 UTC	171.22 KB	no flags	Details

Attachment #135239
journalctl_amdgpu_4.14.0-041400rc7	text/x-log	2017-11-04 21:14:28 UTC	171.65 KB	no flags	Details

Attachment #138230
attachment-10505-0.html	text/html	2018-03-20 22:30:05 UTC	2.77 KB	no flags	Details

<html>
<head>
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<base href="https://bugs.freedesktop.org/">
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<body>
<div dir="auto" style="direction:ltr; margin:0; padding:0; font-family:sans-serif; font-size:11pt; color:black">
As it has failed to attract any developer attention in for two years, I have cancelled the bountysource reward.</div>
<hr tabindex="-1" style="display:inline-block; width:98%">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> bugzilla-daemon@freedesktop.org &lt;bugzilla-daemon@freedesktop.org&gt;<br>
<b>Sent:</b> Saturday, November 4, 2017 10:14:28 PM<br>
<b>To:</b> myhateisblind@hotmail.com<br>
<b>Subject:</b> [Bug 60879] [radeonsi] Tahiti LE: GFX block is not functional, CP is okay</font>
<div>&nbsp;</div>
</div>
<div>
<p></p>
<div><b><a class="bz_bug_link 
          bz_status_REOPENED " title="REOPENED - [radeonsi] Tahiti LE: GFX block is not functional, CP is okay" href="https://bugs.freedesktop.org/show_bug.cgi?id=60879#c172">Comment # 172</a> on
<a class="bz_bug_link 
          bz_status_REOPENED " title="REOPENED - [radeonsi] Tahiti LE: GFX block is not functional, CP is okay" href="https://bugs.freedesktop.org/show_bug.cgi?id=60879">
bug 60879</a> from <span class="vcard"><a class="email" href="mailto:adamczuk@tlen.pl" title="MAD &lt;adamczuk@tlen.pl&gt;"><span class="fn">MAD</span></a>
</span></b>
<pre>Created <span class=""><a href="attachment.cgi?id=135239" name="attach_135239" title="journalctl_amdgpu_4.14.0-041400rc7">attachment 135239</a> <a href="attachment.cgi?id=135239&amp;action=edit" title="journalctl_amdgpu_4.14.0-041400rc7">[details]</a></span>
journalctl_amdgpu_4.14.0-041400rc7

I've had more luck with amdgpu. Well kinda. It finally boots without nomodeset
(starting from 4.13 kernel). But falls back to software rendering (Device:
llvmpipe). It also complains that:
amdgpu 0000:01:00.0: SI support provided by radeon.
amdgpu 0000:01:00.0: Use radeon.si_support=0 amdgpu.si_support=1 to override.

But when I start it with:
modprobe.blacklist=radeon radeon.si_support=0 amdgpu.si_support=1 

screen freezes, gnome doesn't start and it produces output from attachment.
Something about &quot;dead whales&quot;:
lis 04 19:35:39 pc gnome-session-binary[1369]: CRITICAL: We failed, but the
fail whale is dead. Sorry....

There is also something about:
lis 04 19:34:09 pc org.gnome.Shell.desktop[1440]: amdgpu_device_initialize:
Cannot parse ASIC IDs, 0xffffffea./usr/share/libdrm/amdgpu.ids: No such file or
directory</pre>
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Attachment #143276
journalctl-b0-radeonsi-4.20.6.log	text/x-log	2019-02-03 10:01:21 UTC	113.75 KB	no flags	Details

Attachment #143277
Xorg-radeonsi-4.20.6.log	text/x-log	2019-02-03 10:01:51 UTC	36.48 KB	no flags	Details

Attachment #143278
journalctl-b0-amdgpu-4.20.6.log	text/x-log	2019-02-03 10:02:42 UTC	112.46 KB	no flags	Details

Attachment #143279
Xorg-amdgpu-4.20.6.log	text/x-log	2019-02-03 10:03:15 UTC	16.43 KB	no flags	Details

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